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| Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA OOO Order this document by: MC68181 Technical Data MC68181 Advance Information ROAMING FLEXTM chip SIGNAL PROCESSOR The FLEXTM protocol is a multi-speed, high-performance protocol adopted by leading service providers worldwide as a de facto paging standard. The FLEX protocol gives service providers the increased capacity, added reliability, and enhanced pager battery performance they need today. It also provides an upward migration path to the service provider that is completely transparent to the end user. The MC68181 Roaming FLEXTM chip IC is part of a total solution available from Motorola for providing FLEX capabilities in a low-power, low-cost system. The FLEXTM chip simplifies implementation of a FLEX paging device by interfacing with any of several off-the-shelf paging receivers, and any of several off-the-shelf host microcontroller/microprocessors. The primary function of the FLEXTM chip is to process information received and demodulated from a FLEXradio paging channel, select messages addressed to the paging device, and communicate the message information to the host. The host controls receiver channel selection, and interprets the message information in an appropriate manner (numeric, alphanumeric, binary, etc.) and handles all the I/O activity. The FLEXTM chip IC also operates the paging receiver in an efficient power consumption mode and enables the host to operate in a low power mode when monitoring a single channel for message information. Figure 1 shows the MC68181 functional block diagram. EXTS0 EXTS1 SYMCLK Internal Control Unit External Control Unit RESET Freescale Semiconductor, Inc... 2 Vdd Symbol Sync Noise Detector 2 Vss Sync Correlator XTAL EXTAL OSCPD 76.8 kHz Oscillator LOBAT De-Interleaver Error Corrector Control/Status Registers CLKOUT Clock Address Comparator Local Message Filter READY 8 S0-S7 Receiver Control SPI Buffer SPI 4 SPI AA0813 Figure 1 MC68181 Functional Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. (c)1996, 1997 MOTOROLA, INC. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68181 TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 APPENDIX A SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 FLEX SIGNAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 SPI PACKET DESCRIPTION AND HANDLING . . . . . . . . . . . . . B-1 FLEXTM CHIP IC APPLICATION NOTES . . . . . . . . . . . . . . . . . . C-1 Freescale Semiconductor, Inc... APPENDIX B APPENDIX C FOR TECHNICAL ASSISTANCE: Telephone: Internet: 1-800-521-6274 http://www.mot.com/sps/dsp/helpline/messaging Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Note: Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. ii MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Features FEATURES * * * * * * FLEX paging protocol signal processor Sixteen programmable user address words Sixteen temporary addresses Sixteen operator messaging addresses 1600, 3200, and 6400 bits-per-second decoding Any-phase or single-phase decoding Uses standard Serial Peripheral Interface (SPI) in Slave mode Allows low current Stop mode operation of host processor Highly programmable receiver control Real-time clock time base FLEX software fragmentation and group messaging support Real time clock over-the-air update support Compatible with synthesized receivers SSID and NID Roaming support Low Battery Indication (requires external detector) 1.8 to 3.3 V low power operation 32-pin Thin Quad Flat Pack (TQFP) package Backward compatible with MC68175 Freescale Semiconductor, Inc... * * * * * * * * * * * * ADDITIONAL SUPPORT FLEX System Software from Motorola is a family of software components for building worldclass products incorporating messaging capabilities. FLEXstackTM Roaming Software is specifically designed to support the Roaming FLEXTM chip IC. FLEXstack Roaming Software runs on a product's host processor and takes care of communicating with the FLEXTM chip IC, acquiring the proper FLEX channel, and fully interpreting the codewords that are passed to the host from the FLEXTM chip IC. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com iii Freescale Semiconductor, Inc. MC68181 Documentation DOCUMENTATION This document is the primary document supporting the MC68181 FLEXTM chip IC. Documentation is available from: * * * * A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center Through the Motorola Wireless Semiconductor home page on the Internet Freescale Semiconductor, Inc... See the back cover for detailed information. The Motorola Wireless Semiconductors home page on the Internet is the source for the latest information. iv MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS Freescale Semiconductor, Inc... The input and output signals of the MC68181 are organized into six functional groups, as shown in Table 1-1 and as illustrated in Figure 1-1. Table 1-1 MC68181 Functional Signal Groupings Functional Group Power Input and Monitoring Processor Clocks Reset Current Symbol Inputs Serial Peripheral Interface (SPI) Receiver Control Port Number of Signals 7 1 1 2 5 8 Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Figure 1-1 is a diagram of MC68181 signals by functional group. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. MC68181 Power Input and Monitoring MC68181 Power: Input power Ground Low Battery Detect VDD VSS LOBAT 2 4 Current Symbol MSB Current Symbol LSB EXTS1 EXTS0 Freescale Semiconductor, Inc... CLKOUT SYMCLK EXTAL XTAL OSCPD 38.4 kHz Symbol Clock External input External output Oscillator Power Down Serial Peripheral Interface (SPI) SCK SS MOSI MISO READY 8 RESET Hardware Reset Receiver Control Port S0-S7 AA122 Figure 1-1 Signals Identified by Functional Group POWER INPUT AND MONITORING Table 1-2 Power Input, Monitoring, and Control Signals Power Name VDD VSS LOBAT Description Power--VDD is the input power for the IC. Ground--VSS is ground connection for the IC. Low Battery--LOBAT provides an input signal to indicate to the IC when external battery power is going low. (An external voltage sensing circuit is required) 1-2 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Processor Clock PROCESSOR CLOCK Table 1-3 Processor Clock Signals Signal Name CLKOUT SYMCLK Type Output Output State During Reset Indeterminate Indeterminate Signal Description Clock Output--This is typically a 38.4 kHz clock output (derived from 76.8 kHz oscillator). Recovered Symbol Clock--Data is synchronized to the internal clock and this recovered clock output enhances lockon capability by reducing jitter from cable-induced noise. External Clock/Crystal Input--EXTAL interfaces the internal crystal oscillator input to a 76.8 kHz crystal input or other external input clock. External Clock/Crystal Output--This is typically a 76.8 kHz clock output. Oscillator Power Down--This input determines whether the internal oscillator is used. Connect this pin to VSS when using the 76.8 kHz crystal input. Connect this pin to VDD when using an external input clock signal. Freescale Semiconductor, Inc... EXTAL Input Input XTAL OSCPD Output Input Indeterminate Input RESET Table 1-4 Test and Reset Signals Signal Name RESET Type Input State During Reset Input Signal Description Reset--This input is a direct hardware reset on the FLEXTM chip IC. When RESET is asserted low, the FLEXTM chip IC is initialized and placed in the Reset state. CURRENT SYMBOL INPUTS Table 1-5 Interrupt and Mode Control Signal Name EXTS1 EXTS0 Type Input Input State During Reset Input Input Signal Description External Symbol 1--This is the Most Significant Bit (MSB) of the symbol being tested. External Symbol 0--This is the Least Significant Bit (LSB) of the symbol being tested. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-3 Freescale Semiconductor, Inc. MC68181 Serial Peripheral Interface (SPI) SERIAL PERIPHERAL INTERFACE (SPI) Table 1-6 Serial Peripheral Interface (SPI) Signals Signal Name SCK Signal Type Input State during Reset Input Signal Description SPI Serial Clock--The SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if the Slave Select (SS) signal is not asserted. SPI Slave Select--This signal is used to enable the SPI slave for transfer. SPI Master-Out-Slave-In--Since the MC68181 is always a slave device, this is the data input for SPI communications. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. SPI Master-In-Slave-Out--Since the MC68181 is always a slave device, this is the data output for SPI communications. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. SPI Ready--This signal is driven low when the FLEXTM chip IC is ready for an SPI packet. SS Input Input Input Input Freescale Semiconductor, Inc... MOSI MISO Output Tri-stated READY Output Output, driven high RECEIVER CONTROL LINES Table 1-7 Receiver Control Lines Signal Name S0-S7 Signal Type Output State during Reset Tri-stated Signal Description Control Line 0-Control Line 7--These signals are the eight receiver control lines. 1-4 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 2 SPECIFICATIONS INTRODUCTION Freescale Semiconductor, Inc... The MC68181 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. MAXIMUM RATINGS CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VDD). Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-1 Freescale Semiconductor, Inc. MC68181 Thermal characteristics Table 2-1 Maximum Ratings Rating Supply Voltage All input voltages Current drain per pin excluding VDD and VSS Operating temperature range Storage temperature Symbol VDD VIN I TA TSTG Min Max 6 6.5 10 +85 +150 Unit V V mA -0.5 -0.5 -- -30 -65 C C Freescale Semiconductor, Inc... THERMAL CHARACTERISTICS Table 2-2 Thermal Characteristics Characteristic Junction-to-ambient thermal resistance1 Thermal characterization parameter Note: 1. Symbol RJA or JA JT TQFP Value 95 21 Unit C/W C/W Junction-to-ambient thermal resistance is based on measurements on a horizontal, single-sided Printed Circuit Board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Values were measured with the parts mounted on thermal test boards meeting the specification EIA/ JESD51-3. 2-2 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics Characteristics Supply voltage Input voltage Output voltage1 Symbol VDD VI VO VIH Min 1.8 0 0 0.75VDD 0.7 VDD -- 0 -0.25 -10 0.8 VDD -- -- -- -30 -- 0.2VDD 0.1VDD -- -- -- Typ 3.3 -- -- -- -- -- -- -- -- -- -- 100 10 25 -- -- -- -- -- -- Max 3.6 VDD VDD -- -- 0.2VDD 25 0.25 +10 -- 0.3 -- -- 150 0.7VDD -- 0.3VDD +/- 10 -1 1 Unit V V V V V V ns A A V V A pF Freescale Semiconductor, Inc... Input high voltage RESET, SS, SCK, MOSI All other inputs Input low voltage Input transition (rise and fall) time Input leakage current High impedance (off-state) input current (@ 1.44 V /0.3 V) Output high voltage (IOH = -1.0 mA) Output low voltage (IOL = 2.8 mA) Internal Supply Current2 VIL tt IIN ITSI VOH VOL IDD CIN Tj ViT+ ViTVhys IOZ IIL IIH Input capacitance Virtual junction temperature Positive-going threshold voltage3,4 Negative-going threshold Hysteresis (ViT+ - ViT-)3 3-state-output Hi-Z current5 Lower-level input current6 High-level input Note: 1. 2. 3. 4. 5. 6. 7. C V V V A A A voltage3,4 current7 Applies to output buffers This value is for static IDD. Applies to input and bi-directional buffers with hystersis Test condition = CMOS compatible 3-state or open-drain output must be in the high-impedance mode. Specifications only apply with pullup terminator turned off. Specifications only apply with pulldown terminator turned off MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-3 Freescale Semiconductor, Inc. MC68181 AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.2 x VDD in V and a VIH minimum of 0.7 x VDD in V for all inputs. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. MC68181 output levels are measured with the production test machine VOL and VOH reference levels set at 0.3 x VDD in V and 0.6 x VDD in V, respectively. Freescale Semiconductor, Inc... INITIALIZATION TIMING (VDD = 1.8 to 3.6 V, TA = -30 to + 85C) Table 2-4 Initialization Timing Characteristic Oscillator Start-up Time RESET Hold Time RESET High to READY Low Oscillator Warmed Up to READY Low Note: Conditions -- -- -- CL = 50pf Symbol tSTART tRESET tRHRL tOWRL Min -- 200 76,800 -- Max 5 -- 76,800 1 Unit sec ns T sec T is one period of the 76.8 kHz clock source. From power-up, the oscillator start-up time can impact the availability and period of clock strobes. This can affect the actual RESET high to READY low timing. 2-4 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 RESET Timing VDD tSTART Oscillator RESET tRESET Freescale Semiconductor, Inc... READY tOWRL tRHRL AA1221 Figure 2-1 Startup Timing RESET TIMING (VDD = 1.8 to 3.6 V, TA = -30 to 85C) Table 2-5 Reset Timing Characteristic RESET Pulse Width RESET Low to READY High RESET High to READY Low Conditions -- -- Requires stable 76.8 kHz clock source Symbol tRL tRLRH tRHRL Min 200 -- -- Max -- 200 1 Unit ns ns sec RESET tRL READY tRLRH tRHRL AA1222 Figure 2-2 Reset Timing MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-5 Freescale Semiconductor, Inc. MC68181 Serial Peripheral Interface (SPI) Timing SERIAL PERIPHERAL INTERFACE (SPI) TIMING (VDD = 1.8 to 3.6 V, TA = -30 to +85C) Table 2-6 SPI Timing Characteristic Operating Frequency Cycle Time Select Lead Time Conditions -- -- -- -- Previous packet did not program an address word; CL = 50 pf Previous packet programmed an address word; CL = 50 pf -- -- CL = 50pf -- -- CL = 50pf -- CL = 50pf -- -- -- -- 20% to 70% VDD 20% to 70% VDD Symbol fOP tCYC tLEAD1 tLAG1 tRDY tRDY tRH tLEAD2 tLAG2 tSU tHI tAC tDIS tV tHO tSSH tSCKH tSCKL tR tF Min 0 1000 200 200 -- -- 50 200 -- 200 200 0 -- -- 0 200 300 300 Max 1 -- -- -- 80 420 -- -- 200 -- -- 200 300 200 -- -- -- -- 1 1 Unit MHz ns ns ns s s s ns ns ns ns ns ns ns ns ns ns ns s s Freescale Semiconductor, Inc... De-select Lag Time Select-to-Ready Time Select-to-Ready Time Ready High Time Ready Lead Time Not Ready Lag Time MOSI Data Setup Time MOSI Data Hold Time MISO Access Time MISO Disable Time MISO Data Valid Time MISO Data Hold Time SS High Time SCK High Time SCK Low Time SCK Rise Time SCK Fall Time Note: When the host reprograms an address word with a Host-to-FLEXTM chip packet ID > 127 (decimal), there may be an added delay before FLEXTM chip is ready for another packet. 2-6 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Serial Peripheral Interface (SPI) Timing SS tSSH READY tRDY tLEAD1 SCK Tristated MISO tAC MOSI tSU tHI tSCKL D31 tV D31 tHO tSCKH D0 tDIS D0 AA1223 tLEAD2 tCYC tR tF tLAG2 tRH tLAG1 Freescale Semiconductor, Inc... Tristated Figure 2-3 SPI Timing MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-7 Freescale Semiconductor, Inc. MC68181 Serial Peripheral Interface (SPI) Timing Freescale Semiconductor, Inc... 2-8 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION PACKAGING PIN-OUT AND PACKAGE INFORMATION 3 Freescale Semiconductor, Inc... This section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The MC68181 is available in a 32-pin Thin Quad Flat Pack (TQFP) package. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 3-1 Freescale Semiconductor, Inc. MC68181 Pin-out and Package Information TQFP Package Description Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. RESET 24 Freescale Semiconductor, Inc... 17 16 NC S0 S1 S2 S3 S4 S5 NC READY SS 25 S6 S7 SYMCLK SCK VSS Orientation Mark MOSI MISO (Top View) VDD EXTS0 EXTS1 LOBAT CLKOUT 32 1 8 9 NC OSCPD XTAL EXTAL NC VSS VSS VDD VSS AA122 Figure 3-1 MC68181 Thin Quad Flat Pack (TQFP), Top View 3-2 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Pin-out and Package Information S6 S7 16 17 24 25 RESET NC S5 S4 S3 S2 S1 S0 NC READY SS Freescale Semiconductor, Inc... SYMCLK VDD EXTS0 EXTS1 LOBAT SCK VSS (Bottom View) Orientation Mark MISO MOSI NC 9 8 1 32 CLKOUT OSCPD EXTAL XTAL VSS VSS VSS VDD NC AA122 Figure 3-2 MC68181 Thin Quad Flat Pack (TQFP), Bottom View MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 3-3 Freescale Semiconductor, Inc. MC68181 Pin-out and Package Information Table 3-1 Signal by Pin Number Pin # Signal Name 1 2 3 4 5 NC1 OSCPD VDD VSS2 XTAL EXTAL VSS2 VSS2 1. 2. Pin # Signal Name Pin # Signal Name 9 10 11 12 13 14 15 16 NC1 LOBAT EXTS1 EXTS0 VDD SYMCLK S7 S6 17 18 19 20 21 22 23 24 NC1 S5 S4 S3 S2 S1 S0 RESET Pin # Signal Name 25 26 27 28 29 30 31 32 NC1 READY SS SCK VSS2 MOSI MISO CLKOUT Freescale Semiconductor, Inc... 6 7 8 Note: NC indicates reserved pins. These pins must not be connected to any external line. To ensure proper chip operation, all VSS pins must be connected to GND. Table 3-2 Signal by Name Signal Name CLKOUT EXTAL EXTS0 EXTS1 LOBAT MISO MOSI NC Pin # Signal Name Pin # Signal Name 32 6 12 11 10 31 30 1 NC NC NC OSCPD READY RESET S0 S1 9 17 25 2 26 24 23 22 S2 S3 S4 S5 S6 S7 SCK SS Pin # Signal Name Pin # 21 20 19 18 16 15 28 27 SYMCLK VDD VDD VSS VSS VSS VSS XTAL 14 3 13 4 7 8 29 5 3-4 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Pin-out and Package Information A A1 32 25 4X 1 -TB B1 8 -UV P DETAIL Y 17 AE V1 AE DETAIL Y 9 Freescale Semiconductor, Inc... -Z9 S1 S 4X 0.20 AC T-U Z G -ABSEATING PLANE DETAIL AD -ACBASE METAL N F 8X D 0.20 M R J M AC T-U Z 0.10 AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12 REF 0.090 0.160 0.400 BSC 1 5 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF CE SECTION AE-AE H W X DETAIL AD GAUGE PLANE K Q 0.250 DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X CASE 873A-02 ISSUE A DATE 12/16/93 Figure 3-3 32-pin Thin Quad Flat Pack (TQFP) Mechanical Information MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com -T-, -U-, -Z- 0.20 AB T-U Z 3-5 Freescale Semiconductor, Inc. MC68181 Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding MC68181 packaging is available by facsimile through Motorola's MfaxTM system. Call the following number to obtain information by facsimile: (602) 244-6591 The Mfax automated system requests the following information: Freescale Semiconductor, Inc... * * The receiving facsimile telephone number including area code or country code The caller's Personal Identification Number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. * The type of information requested: - - - - Instructions for using the system A literature order form Specific part technical information or data sheets Other information described by the system messages A total of three documents may be ordered per call. The MC68181 32-pin TQFP package mechanical drawing is referenced as 873A-02. 3-6 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 4 DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS Freescale Semiconductor, Inc... An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: T J = T A + ( P D x R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board, or otherwise change the thermal dissipation capability of the area surrounding the device on a Printed Circuit Board. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the Printed Circuit Board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the Printed Circuit Board to which the package is mounted. Again, if the MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 4-1 Freescale Semiconductor, Inc. MC68181 Thermal Design Considerations estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD. * Freescale Semiconductor, Inc... * As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4-2 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Application Design Considerations APPLICATION DESIGN CONSIDERATIONS The FLEXTM chip IC connects to a receiver capable of converting a four-level FSK-encoded audio signal into a 2-bit digital signal. The FLEXTM chip IC has eight receiver control lines used for warming up and shutting down a receiver in stages. The FLEXTM chip IC has dual bandwidth control signals for two post detection filter bandwidths for receiving the two symbol rates of the FLEX signal. The FLEXTM chip IC has the ability to detect a low battery signal during the receiver control sequences. It interfaces to a host MCU through a standard SPI. It has a 38.4 kHz clock output capable of driving other devices. It has a 1 minute timer that offers low power support for time of day function on the host. Figure 4-1 shows a typical application block diagram. IF STAGES LNA MRF1047T1 MRF927T1 MRF947T1 Mixer/Amp MMBR961LT1 MR947T1 MC13143 FM IF MC3374 MC13150 ADC 2-bit FLEXTM A/O FLEXTM Subsystem MC68181FDB Data Rec Audio VCO/Buffer Frequency Synthesizers Freescale Semiconductor, Inc... 2/4 level FSK RF In MC68181 SPI Host Processor PLL MRFIC0916 MRFIC0915 MRF947T1 MRF927T1 MRF2947AT1 MC141592 SPI MC68HC08 MC68HC11/12 MC68328 MPC821 DSP56L811 AA1216 Figure 4-1 Roaming FLEXTM chip System Block Diagram MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 4-3 Freescale Semiconductor, Inc. MC68181 Application Design Considerations Figure 4-2 shows a recommended circuit for a 76.8 kHz crystal input. Ex: UT200 Crystal Sanyo EXTAL R2 10 M C1 10 pF R1 0 C2 10 pF Freescale Semiconductor, Inc... XTAL Note: R1 can be increased in size to be used as a current limiter, if needed. AA1069 Figure 4-2 Input Circuit for 76.8 kHz Crystal Appendix A of this document provides a background of the FLEX signal protocol. Appendix B provides a description of the way in which the MC68181 FLEXTM chip IC handles packets through the SPI, including sections that describe transfer from the host to the decoder from the decoder to the host. Appendix C provides a sample application to illustrate how the MC68181 FLEXTM chip IC might be used in an application. 4-4 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 5 ORDERING INFORMATION Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information Freescale Semiconductor, Inc... Part MC68181 Supply Voltage 2/3 V Package Type Thin Quad Flat Pack (TQFP) Pin Count 32 Frequency (kHz) 76.8 Order Number MC68181FA MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 5-1 Freescale Semiconductor, Inc. MC68181 Freescale Semiconductor, Inc... 5-2 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. APPENDIX A FLEX OVERVIEW This appendix gives an overview of the FLEX protocol as it pertains to the Roaming FLEX chip IC. This is only an overview and in the event that there is contradictory information, the FLEX Protocol Specification prevails. This overview is derived from Issue G1.8 of the FLEX Protocol Specification. Freescale Semiconductor, Inc... FLEX SIGNAL STRUCTURE As shown in Figure A-1, a FLEX signal is transmitted on a radio channel and consists of a series of four-minute cycles, each cycle having 128 frames at 1.875 seconds per frame. A pager may be assigned to process any number of these frames. Any unassigned frames are not processed, thus reducing power required for signal processing and extending battery life. If required, however, the pager may temporarily process more complex information, because individual FLEX cycles can assign additional frames dynamically using collapse, fragmentation, temporary addressing, or carry-on information within the FLEX signal. One Cycle = 4 Minutes Frame 127 Frame 0 Frame 1 Frame Frame 2 3 Frame 4 Frame 125 Frame 126 Frame 127 One Frame = 1.875 s. Sync 1 Frame Info Sync 2 Block 0 Word Number 0 to 7 One Block = 160 ms Block 9 Word Number 72 to 79 Block 10 Word Number 80 to 87 AA1226 Figure A-1 FLEXTM Signal Structure MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-1 Freescale Semiconductor, Inc. MC68181 FLEX Frame Structure FLEX FRAME STRUCTURE As shown in Figure A-1 on page A-1, each FLEX frame consists of: * * Synchronization portion Data portion--Eleven data blocks lasting 160 milliseconds each Frame Synchronization Portion Freescale Semiconductor, Inc... The synchronization portion consists of: * * First synchronization signal at 1600 bps Frame Information Word including: - - * Frame Number 0-127 (7 bits) Cycle Number 0-14 (4 bits) Second synchronization signal at the data rate of the interleaved portion. FIRST SYNCHRONIZATION SIGNAL The first synchronization signal is transmitted at 1600 bps and provides a signal to lock onto the specific frame. FRAME INFORMATION WORD The Frame Information Word transmits 11 bits that are divided into a 7-bit frame number and a 4-bit cycle number. This allows the pager to identify the frame and the cycle in which it resides uniquely. SECOND SYNCHRONIZATION SIGNAL The second synchronization signal indicates the rate at which the data portion is transmitted, 1600, 3200 or 6400 bits per second. A-2 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Frame Structure The 1600 bps rate is transmitted as a single phase of information (A), as shown in Figure A-2 on page A-3, at 1600 symbols per second using 2-level Frequency Shift Keyed (FSK) modulation. One Cycle = 4 Minutes Frame 127 Frame 0 Frame 1 Frame Frame 2 3 Frame 4 Frame 125 Frame 126 Frame 127 Freescale Semiconductor, Inc... One Frame = 1.875 s. Sync 1 Frame Info Sync 2 Block 0 Word Number 0 to 7 One Block = 160 ms Block 9 Word Number 72 to 79 Block 10 Word Number 80 to 87 1600 BPS PHASE A BIW Address Field Vector Field Message Field Idle Field AA1227 Figure A-2 FLEXTM Signal Structure for 1600 BPS MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-3 Freescale Semiconductor, Inc. MC68181 FLEX Frame Structure The 3200 bps rate is transmitted as two concurrent phases of information (A and C), as shown in Figure A-3, at either: * * 1600 symbols per second using 4-level FSK modulation, or 3200 symbols per second using 2-level FSK modulation. One Cycle = 4 Minutes Frame 127 Frame 0 Frame 1 Frame Frame 2 3 Frame 4 Frame 125 Frame 126 Frame 127 Freescale Semiconductor, Inc... One Frame = 1.875 s. Sync 1 Frame Info Sync 2 Block 0 Word Number 0 to 7 One Block = 160 ms Block 9 Word Number 72 to 79 Block 10 Word Number 80 to 87 3200 BPS PHASE A PHASE C BIW BIW Address Field Address Field Vector Message Field Idle Field Field Vector Message Field Idle Field Field AA1228 Figure A-3 FLEXTM Signal Structure for 3200 BPS A-4 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Frame Structure The 6400 bps rate is transmitted as four concurrent phases of information (A,B, C, and D), as shown in Figure A-4, at 3200 symbols per second using 4-level FSK modulation. One Cycle = 4 Minutes Frame 127 Frame 0 Frame 1 Frame Frame 2 3 Frame 4 Frame 125 Frame 126 Frame 127 Freescale Semiconductor, Inc... One Frame = 1.875 s. Sync 1 Frame Info Sync 2 Block 0 Word Number 0 to 7 One Block = 160 ms Block 9 Word Number 72 to 79 Block 10 Word Number 80 to 87 PHASE A 6400 BPS PHASE B PHASE C PHASE D Address Vector Message Field Idle Field Field Field Address Vector Message Field Idle Field BIW Field Field Address Vector Idle Message Field BIW Field Field Field Address Vector Message Field BIW Field Field BIW AA1229 Figure A-4 FLEXTM Signal Structure For 6400 BPS Frame Data Portion As noted above, there are eleven data blocks following the frame synchronization portion of each frame. Each block has eight interleaved words per phase, numbered 0-87 contiguously for all eleven blocks, in every frame. Each word has information that allows for bit error correction and detection contained within an error correcting code. Each of the eighty-eight words in each phase is organized into the following five fields: MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-5 Freescale Semiconductor, Inc. MC68181 FLEX Frame Structure * * * * * Block information field Address field Vector field Message field Idle field The boundaries between the fields are independent of the block boundaries. Furthermore, at 3200 and 6400 bps, the information in one phase is independent of the information in a concurrent phase, and the boundaries between the fields of one phase are unrelated to the boundaries between the fields in a concurrent phase. Freescale Semiconductor, Inc... BLOCK INFORMATION FIELD The block information field may contain information words for determining time and date information and certain paging system information. ADDRESS FIELD The address field contains addresses assigned to paging devices. Addresses are used to identify information sent to individual paging devices and/or groups of paging devices. An address may be either a "short" one word address or a "long" two word address. Information in the FLEX signal may indicate that an address is a priority address. An address may be a "tone only" address, in which case there is no additional information associated with the address. VECTOR FIELD The vector field consists of a series of vector words. Depending upon the type of message, a vector word (or words in the case of a long address) may either contain all of the information necessary for the message, or indicate the location of message words in the message field comprising the message information. If an address is not a tone only address, then there is an associated vector word in the vector field. Information in the FLEX signal indicates the location of the vector word. Short addresses have one associated vector word and long addresses two associated vector words. A pager may go to low power mode at the end of the address field if its address(es) is (are) not detected, thus resulting in battery savings. MESSAGE FIELD The message field consists of a series of information words containing message information. The message information may be formatted in ASCII, BCD, or binary depending upon the message type. The following sections provide a detailed description of the various types of information words that may be used in the message field. IDLE FIELD The idle field is used to separate blocks. A-6 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions FLEX MESSAGE WORD DEFINITIONS Numeric Data Message The following tables describe the bit format of the numeric messages. The 4-bit numeric characters of the message are designated as lower case letters a, b, c, d, etc. Table A-1 Standard (V = 011) or Special Format (V = 100) Numeric Vectors Freescale Semiconductor, Inc... Message Word 1st 2nd 3rd 4th 5th 6th 7th 8th i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 K4 K5 a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 d0 d1 d2 d3 e0 e1 e2 e3 f0 f1 f2 f3 g0 g1 g2 g3 h0 h1 h2 h3 i0 l1 r2 l2 r3 l3 i1 i2 i3 j0 j1 j2 j3 k0 k1 k2 k3 l0 q1 q2 q3 r0 r1 m0 m1 m2 m3 n0 n1 n2 n3 o0 o1 o2 o3 q0 t1 t2 t3 u0 u1 u2 u3 v0 v1 s0 s1 s2 s3 t0 v2 v3 w0 w1 w2 w3 y0 y1 y2 y3 z0 z1 z2 z3 A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 E0 E1 E2 E3 F0 F1 F2 F3 G0 G1 G2 G3 H0 H1 H2 H3 I0 I1 I2 I3 J0 J1 J2 J3 V0 V1 V2 V3 L0 L1 L2 L3 M0 M1 M2 M3 O0 O1 O2 O3 P0 P1 P2 P3 Q0 Q1 Q2 Q3 T0 T1 T2 T3 U0 U1 Table A-2 Numbered (V = 111) Numeric Vector Message Word 1st 2nd 3rd 4th 5th 6th 7th 8th i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 K4 K5 N0 N1 N2 N3 N4 N5 R0 S0 a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 d0 d1 d2 d3 e0 e1 e2 e3 f0 i0 i1 i2 i3 j0 j1 j2 j3 f1 f2 f3 g0 g1 g2 g3 h0 h1 h2 h3 l1 r2 l2 r3 l3 m0 m1 m2 m3 n0 t1 k0 k1 k2 k3 l0 r1 n1 n2 n3 o0 o1 o2 o3 q0 q1 q2 q3 r0 t2 t3 s0 s1 s2 s3 t0 u0 u1 u2 u3 v0 v1 v2 v3 w0 w1 w2 w3 y0 y1 y2 y3 z0 z1 z2 z3 A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 E0 E1 E2 E3 F0 F1 F2 F3 G0 G1 G2 G3 H0 H1 H2 H3 I0 I1 I2 I3 J0 J1 J2 J3 V V1 V2 V3 L0 L1 L2 L3 M0 M1 M2 M3 O0 O1 O2 O3 P0 P1 P2 P3 Q0 Q1 MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-7 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-3 Numeric Message Bit Definitions Symbol K Definition 6-bit Message Check Character (First 4 bits are in the vector word)--This check character is calculated by initializing the message check character (K) to 0 and summing the information bits of each code word in the message, (including control information and termination characters and bits in the last message word) to a check sum register. The information bits of each word are broken into three groups: the first is the 8 bits comprising i0 through i7, the second group comprises bits i8 through i15, and the third group comprises bits i16 through i20. Bits i0, i8, and i16 are the LSBs of each group. The binary sum is calculated, and the result is shortened to the eight Least Significant Bits. The two Most Significant Bits are shifted 6 bits to the right and summed with the six Least Significant Bits to form a new sum. This resultant sum is one's complemented with the six LSBs of the result being transmitted as the message check character. Message Number--When the system supports message retrieval, the system controller assigns message numbers (for each paging address separately) starting at zero and progressing up to a maximum of sixty-three in consecutive order. The actual maximum roll over number is defined in the pager code plug to accommodate values set in the system infrastructure. When message numbers are not received in order, the subscriber should assume a message has been missed. The subscriber or the pager may determine the missing message number(s) allowing a request to be made for retrieval. When a normal unnumbered numeric message is received (Message Retrieval Flag = 0), it is not to be included in the missed message calculation. Message Retrieval Flag--When this bit is set to 1, the pager expects to see messages numbered in order (each address numbered separately). Detection of a missing number indicates a missed message. A message received with R = 0 is allowed to be out of order and shall not cause the pager to indicate that a message has been missed. Special Format--In the numbered message format, this bit set to 1 indicates that a special display format should be used. Freescale Semiconductor, Inc... N R S MESSAGE FILL RULES For numeric messages of thirty-six characters or less (thirty-four characters if numbered), fewer than eight code words on the channel are required. Only code words containing the numeric message are to be transmitted. The space character ($C) should be used to fill any unused 4-bit characters in the last word and zeros to fill any remaining partial characters. The check sum is correspondingly shortened to include only the code words comprising the shortened message along with the space and fill characters used to fill in the last word. SPECIAL FORMAT NUMERIC Spaces and dashes as specified by the host are inserted into the received message. This feature in certain markets saves the transmission of an additional word on the channel. As an example, in the U.S. market a 10-character string (area code plus telephone number) fits into two message words; if the dashes or parentheses are to be A-8 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions included in the message, a third message word on the channel is required. The actual placement can be programmed into the paging device and can vary between markets. Hex/Binary Message The following tables describe the bit format of the Hex/Binary messages. The data of the message is designated as lower case letters a, b, c, d, etc. Hex/binary messages can be sent as fragments. The service provider has the option of dividing the message into several pieces and sending the separate pieces at any time within a given time period. Table A-4 Vector Type V = 110 First Only Fragment Message Word 1st 2nd 3rd 4th 5th 6th ... nth i i i i i i i i i i i i i i i i i i i i i i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 Freescale Semiconductor, Inc... K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 C0 F0 F1 N0 N1 N2 N3 N4 N5 R0 M0 D0 H0 B0 B1 B2 B3 s0 s1 s2 s3 s4 S0 S1 S2 S3 S4 S5 S6 S7 a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 d0 d1 d2 d3 e0 e1 e2 e3 f0 f1 f2 f3 g0 g1 g2 g3 h0 h1 h2 h3 i0 l1 r2 l2 r3 l3 i1 i2 i3 j0 j1 j2 j3 k0 k1 k2 k3 l0 q3 r0 r1 m0 m1 m2 m3 n0 n1 n2 n3 o0 o1 o2 o3 q0 q1 q2 t1 t2 t3 u0 u1 u2 u3 v0 v1 v2 v3 s0 s1 s2 s3 t0 Table A-5 Vector Type V=110 All Other Fragments Message Word 1st 2nd 3rd 4th 5th ... nth i i i i i i i i i i i i i i i i i i i i i i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 C0 F0 F1 N0 N1 N2 N3 N4 N5 a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 d0 d1 d2 d3 e0 e1 e2 e3 f0 f1 f2 f3 g0 g1 g2 g3 h0 h1 h2 h3 i0 l1 r2 l2 r3 l3 i1 i2 i3 j0 j1 j2 j3 k0 k1 k2 k3 l0 q3 r0 r1 m0 m1 m2 m3 n0 n1 n2 n3 o0 o1 o2 o3 q0 q1 q2 t1 t2 t3 u0 u1 u2 u3 v0 v1 v2 v3 s0 s1 s2 s3 t0 MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-9 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-6 Hex/Binary Message Bit Definitions Symbol1 K Definition 12-bit Fragment Check Sum--This check sum is calculated by initializing the Fragment Check Sum field (K) to 0 and calculating a sum over the information bits of each code word in the message fragment (including control information and termination characters/bits in the last fragment word). This sum requires that the information bits of each word be broken into three groups: the first is the 8 bits comprising i0 through i7, the second group comprises bits i8 through i15, and the third group comprises bits i16 through i20. Bits i0, i8, and i16 are the LSBs of each group. The binary sum is calculated over all code words in the fragment, the one's complement of the sum is determined, and the twelve LSBs of the result is placed into the Fragment Check Sum field to be transmitted at the beginning of the fragment. 1-bit Message Continued Flag--When set to 1, this flag indicates fragments of this message are to be expected in any or possibly all of the following frames until a fragment with C = 0 is found. The longest message that fits into a frame is eighty-four code words. Three alpha characters per word yields a maximum message of 252 characters in a frame, assuming no other traffic. Messages longer than this value must be sent as several fragments. 2-bit Message Fragment Number--This is a modulo 3 message fragment number that is incremented by 1 in successive message fragments. The initial fragment starts at 11 and each following fragment is incremented by 1 modulo 3, (11, 00, 01, 10, 00, 01, 10, 00, etc.). The 11 state (after the initial fragment) is skipped in this process to avoid confusion with the single fragment of a non-continued message. The final fragment is indicated by the Message Continued Flag being reset to 0. Message Number--When the system supports message retrieval the system controller assigns message numbers (for each paging address separately) starting at 0 and progressing up to a maximum of 63 in consecutive order. The actual maximum roll over number is defined in the pager code plug to accommodate values set in the system infrastructure. When message numbers are not received in order, the subscriber should assume a message has been missed. The subscriber or the pager may determine the missing message number(s) allowing a request to be made for retrieval. When a normal unnumbered numeric message is received (message retrieval flag is equal to 0), it is not to be included in the missed message calculation. This number is also used to identify fragments of the same message. Multiple messages to the same address must have separate message numbers. An exception to this rule is the header message tied to a transparent message, each with the same message number. Message Retrieval Flag--When this bit is set to 1, the pager expects to see messages numbered in order (each address numbered separately). Detection of a missing number indicates a missed message. A message received with R = 0 is allowed to be out of order and not cause the pager to indicate that a message has been missed. 1-bit Mail Drop Flag--When set to 1, this bit indicates the message is to be stored in a special area in memory. It automatically writes over existing data in that memory space. Freescale Semiconductor, Inc... C F N R M A-10 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-6 Hex/Binary Message Bit Definitions (Continued) Symbol1 D 1-bit Display Direction Field-- * D = 0--Display left to right * D = 1--Display right to left (valid only when data sent as characters (i.e., Blocking Length not equal 0001)). H 1-bit Header Message-- * H = 1--Indicates that this message is a header to a following transparent message of the same message number * B H = 0--Implies message is not a header Definition Freescale Semiconductor, Inc... 4-bit Blocking Length--This bit field indicates the number of bits per character. * B3B2B1B0 = 0001--1 bit per character (binary/transparent data) * * B3B2B1B0 = 1111--15 bits per character B3B2B1B0 = 0000--16 bits per character Data with blocking length other than 1 is assumed to be displayed on a character by character basis. (default value = 0001) s S 5-bit Field Reserved for future use--Default value = 00000 8-bit Signature Field--The signature is defined to be the one's complement of the binary sum over the total message taken 8 bits at a time prior to formatting into fragments. It would be equivalent to a binary sum starting with the first 8 bits directly following the signature field (b3b2b1b0a3a2a1a0 + d3d2d1d0c3c2c1c0 and so on) and continuing all the way to the last valid data bit in the last word of the last fragment. The 8 Least Significant Bits of the result are inverted (one's complement) and transmitted as the message signature.2 1. 2. Fields R through S are only in the first fragment of a message. The fields K through N make up the first word of every fragment in a long message. This sum does not include any termination bits and should be calculated directly on the message as received by the terminal. The device generating the signature should be able to calculate before the fragmenting boundaries are determined. Note: MESSAGE CONTENT Starting with the first character of the third word in the message (second word in the remaining fragments), each 4-bit field represents one of any of the sixteen possible combinations with no restrictions (data may be binary). FRAGMENT TERMINATION Unused bits in the last message word of a fragment are filled with all 0s or all 1s, depending on the last valid data bit. This choice is always the opposite polarity of the last valid data bit. For first fragments and inner fragments of a multi-fragment MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-11 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions message, the message is interrupted (stopped) on the last full character boundary in the last code word in the fragment. Any unused bits follow the rule just stated. The final fragment follows the above rules except when the last character is all 1s or all 0s and it exactly fills the last code word. In this case, an additional word must be sent of opposite polarity of all 1s or all 0s to signify the position of the last character, thus allowing that last character to be an all 1s or an all 0s character pattern. Note: This is always the case when a binary message ends in the last bit of the last word. MESSAGE HEADER Freescale Semiconductor, Inc... A message header is designated by setting the H bit to 1. This is a displayable tag associated with a transparent non-displayable data message. The tag and the associated message are complete in themselves. The pager associates the header message with the data file based on the two having the same message number and being sent in sequence (header first followed by data file). Alphanumeric Message The following tables describe the bit format of the alphanumeric messages. The 7-bit characters of the message are designated as lower case letters a, b, c, d, etc. Alphanumeric messages can be sent as fragments. The service provider has the option of dividing the message into several pieces and sending the separate pieces at any time within a given time period. Table A-7 Vector type V = 101 First Only Fragment Message Word 1st 2nd 3rd 4th 5th ... nth i i i i i i i i i i i i i i i i i i i i i i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 C0 F0 F1 N0 N1 N2 N3 N4 N5 R0 M0 S0 S1 S2 S3 S4 S5 S6 a0 a1 a2 a3 a4 a5 a6 b0 b1 b2 b3 b4 b5 b6 c0 c1 c2 c3 c4 c5 c6 d0 d1 d2 d3 d4 d5 d6 e0 e1 e2 e3 e4 e5 e6 f0 i0 f1 i1 f2 i2 f3 i3 f4 i4 f5 i5 f6 i6 g0 g1 g2 g3 g4 g5 g6 h0 h1 h2 h3 h4 h5 h6 j0 j1 j2 j3 j4 j5 j6 k0 k1 k2 k3 k4 k5 k6 A-12 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-8 Vector type V = 101 Other Fragment Message Word i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 1st 2nd 3rd 4th K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 C0 F0 F1 N0 N1 N2 N3 N4 N5 U0 V0 a0 a1 a2 a3 a4 a5 a6 b0 b1 b2 b3 b4 b5 b6 c0 c1 c2 c3 c4 c5 c6 d0 d1 d2 d3 d4 d5 d6 e0 e1 e2 e3 e4 e5 e6 f0 g0 g1 g2 g3 g4 g5 g6 h0 h1 h2 h3 h4 h5 h6 i0 j0 j1 j2 j3 j4 j5 j6 k0 k1 k2 k3 k4 k5 k6 l0 f1 i1 l1 f2 i2 l2 f3 i3 l3 f4 i4 l4 f5 i5 l5 f6 i6 l6 Freescale Semiconductor, Inc... 5th ... nth i i i i i i i i i i i i i i i i i i i i i Table A-9 Alphanumeric Message Bit Definitions Symbol K Definition 10-bit Fragment Check Character--This check character is calculated by initializing the fragment check character (K) to 0 and summing the information bits of each code word in the message fragment (including control information and termination characters and bits in the last message word) to a check sum register. The information bits of each word are broken into three groups: the first is the 8 bits comprising i0 through i7, the second group comprises bits i8 through i15, and the third group comprises bits i16 through i20. Bits i0, i8, and i16 are the LSBs of each group. The binary sum is calculated, the one's complement of the sum is determined, and the ten LSBs of the result is transmitted as the message check character. 1-bit Message Continued Flag--When set, this flag indicates fragments of this message are to be expected in following frames. The longest message that fits into a frame is 84 code words total. Three alpha characters per word yields a maximum message of 252 characters in a frame, assuming no other traffic. Messages longer than this value must be sent as several fragments. 2-bit Message Fragment Number--This is a modulo 3 message fragment number that is incremented by 1 in successive message fragments. Initial fragments start at 11 and increment 1 for each successive fragment. The 11 state (after the start fragment) is skipped in this process to avoid confusion with an initial fragment of a non-continued message. The final fragment is indicated by Message Continued Flag being cleared. C F MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-13 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-9 Alphanumeric Message Bit Definitions (Continued) Symbol N Definition Message Number--When the system supports message retrieval, the system controller assigns message numbers (for each paging address separately) starting at 0 and progressing up to a maximum of 63 in consecutive order. The actual maximum roll over number is defined in the pager code plug to accommodate values set in the system infrastructure. When message numbers are not received in order, the subscriber should assume a message has been missed. The subscriber or the pager may determine the missing message number(s), allowing a request to be made for retrieval. When a normal unnumbered numeric message is received (message retrieval flag is equal to 0), it is not to be included in the missed message calculation. This number is also used to identify fragments of the same message. Multiple messages to the same address must have separate message numbers. Message Retrieval Flag--When this bit is set, the pager expects to see messages numbered in order (each address numbered separately). Detection of a missing number indicates a missed message. A message received with R = 0 is allowed to be out of order and not cause the pager to indicate that a message has been missed. 1-bit Mail drop Flag--When set, this flag indicates the message is to be stored in a special area in memory. It automatically writes over existing data in that memory space. 7-bit Signature Field--The signature is defined to be the one's complement of the binary sum over the total message (all fragments) taken 7 bits at a time (on alpha character boundary) starting with the first 7 bits directly following the signature field (a6a5a4a3a2a1a0, b6b5b4b3b2b1b0, etc.). The seven Least Significant Bits of the result are transmitted as the message signature. Fragmentation control bits--This field exists in all fragments except the first fragment. It is used to support character position tracking in each fragment when symbolic characters (characters made up of 1, 2, or 3 ASCII characters) are transmitted using the Alphanumeric message type. The default value for the U, V pair is 0, 0. See Enhanced Fragmentation Rules on page A-15 for more information. Freescale Semiconductor, Inc... R M S U, V MESSAGE CONTENT Starting with the second character of the second word in the message (1st character of the second word in all remaining fragments), each 7-bit field represents Standard ASCII (ISO 646-1983E) characters with options for certain International characters. MESSAGE TERMINATION The ASCII character ETX (03) should be used to fill any unused 7-bit characters in a word. In the case where symbolic characters are being transmitted, special rules for fragment and message termination are defined in the following information on Alphanumeric Message Rules for Symbolic Characters Sets. A-14 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions ALPHANUMERIC MESSAGE RULES FOR SYMBOLIC CHARACTERS SETS In the past, paging protocols have supported symbolic characters (e.g., Chinese, Kanji, etc.) using a 7-bit ASCII protocol. When the FLEX Alphanumeric mode is used to carry this same signaling format, special fragmenting rules are required to maintain character boundaries, so performance is optimized under poor signal conditions. The following rules allow character positions within a fragment to be determined when prior fragments are missing. ENHANCED FRAGMENTATION RULES * The pager must recognize 0 1 0 1 Freescale Semiconductor, Inc... * * U0 0 0 1 1 Definition EF not supported in controller Reserved (for a second alternate character mode) Default Character Mode--start position 1 Alternate Character Mode--start position 1 When the EF field is 00, the pager decodes messages, allowing characters to be split between fragments. When the U, V field is not 0, 0, each fragment starts on a character boundary with the character mode defined by the above table. SECURE MESSAGE The following tables describe the bit format of the secure messages. The 7-bit characters of the message are designated as lower case letters a, b, c, d, etc. Secure messages can be sent as fragments. The service provider has the option of dividing the message into several pieces and sending the separate pieces at any time within a given time period. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-15 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-11 Vector type V = 000 All Fragments Message Word 1st 2nd 3rd 4th i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 C0 F0 F1 N0 N1 N2 N3 N4 N5 s0 s1 a0 a1 a2 a3 a4 a5 a6 b0 b1 b2 b3 b4 b5 b6 c0 c1 c2 c3 c4 c5 c6 d0 d1 d2 d3 d4 d5 d6 e0 e1 e2 e3 e4 e5 e6 f0 g0 g1 g2 g3 g4 g5 g6 h0 h1 h2 h3 h4 h5 h6 i0 j0 j1 j2 j3 j4 j5 j6 k0 k1 k2 k3 k4 k5 k6 l0 f1 i1 l1 f2 i2 l2 f3 i3 l3 f4 i4 l4 f5 i5 l5 f6 i6 l6 Freescale Semiconductor, Inc... 5th ... nth i i i i i i i i i i i i i i i i i i i i i Table A-12 Secure Message Bit Definitions Symbol K Definition 10-bit Fragment Check Character--This check character is calculated by initializing the fragment check character (K) to 0 and summing the information bits of each code word in the message fragment (including control information and termination characters and bits in the last message word) to a check sum register. The information bits of each word are broken into three groups: the first is the 8 bits comprising i0 through i7, the second group comprises bits i8 through i15, and the third group comprises bits i16 through i20. Bits i0, i8, and i16 are the LSBs of each group. The binary sum is calculated, the one's complement of the sum is determined, and the ten LSBs of the result is transmitted as the message check character. 1-bit Message Continued Flag--When set, the Message Continued Flag indicates fragments of this message are to be expected in following frames. The longest message that fits into a frame is 84 code words total. Three alpha characters per word yields a maximum message of 252 characters in a frame, assuming no other traffic. Messages longer than this value must be sent as several fragments. 2-bit Message Fragment Number--This is a modulo 3 message fragment number that is incremented by 1 in successive message fragments. Initial fragments start at 11 and increment 1 for each successive fragment. The 11 state (after the start fragment) is skipped in this process to avoid confusion with an initial fragment of a non-continued message. The final fragment is indicated by Message Continued Flag being cleared. C F A-16 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-12 Secure Message Bit Definitions Symbol N Definition Message Number--When the system supports message retrieval, the system controller assigns message numbers (for each paging address separately) starting at 0 and progressing up to a maximum of 63 in consecutive order. The actual maximum roll over number is defined in the pager code plug to accommodate values set in the system infrastructure. When message numbers are not received in order, the subscriber should assume a message has been missed. The subscriber or the pager may determine the missing message number(s) allowing a request to be made for retrieval. When a normal unnumbered numeric message is received (message retrieval flag is equal to 0), it is not to be included in the missed message calculation. This number is also used to identify fragments of the same message. Multiple messages to the same address must have separate message numbers. Spare Bit--not used and set to 0 Freescale Semiconductor, Inc... s MESSAGE CONTENT Starting with the first character of the second word in the message (and 1st character of all remaining fragments), each 7-bit field represents Standard ASCII (ISO 6461983E) characters with options for certain International characters. MESSAGE TERMINATION The ASCII character ETX (03) should be used to fill any unused 7-bit characters in a word. FLEX Encoding and Decoding Rules The encoding and decoding rules identify the minimum requirements that must be met by the paging device, paging terminal, or other encoding equipment to properly format a FLEX data stream for RF transmission and to successfully decode it. FLEX ENCODING RULES * The stability of the encoder clock used to establish time positions of FLEX frames must be no worse than 25 ppm (including worst case temperature and aging effects). A maximum of two occurrences of an identical individual or radio group address is allowed in any frame for unfragmented messages. This rule applies across all phases in a multi-phase frame. For example, for decoding devices that support any-phase addressing, an any-phase address may appear at once in two different phases in a single multi-phase frame. Once an individual or radio group address is used to begin transmitting a fragmented message, that same address must not be used to start a new * * MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-17 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions fragmented transmission until the first fragmented transmission has been completed. * For the duration of time that an individual or radio group address is being used to send a fragmented message, that same address must not appear more than once in any frame to send an unfragmented message. Once a specific dynamic group address (temporary address) is assigned to a group, it must not be reused until its associated message has been transmitted in its entirety. Given this constraint, the same dynamic group address can only appear once in any frame. A dynamic group address cannot be used to set up a second dynamic group. Messages using any of the three defined numeric vectors (V2V1V0 = 011, 100, and 111) cannot be fragmented, and thus must be completely contained in a single frame. Fragments of the same message must be sent at a frequency of at least 1 every 32 frames (i.e., at least once a minute) or 1 every 128 frames (i.e., at least once every 4 minutes) as specified by the service provider. Enhanced message fragmenting for symbolic character transmission requires that the encoder track character boundaries within each fragment in order to avoid character splitting. Message numbering as an optional feature is offered by some carriers and available on an individual subscriber basis. Message numbers must be assigned sequentially in ascending order. Message number sequences must be separately maintained for each individual and radio group address. Message numbers are not used (retrieval message number disabled) in conjunction with a dynamic group address. When a missed message is re-transmitted from message retrieval storage, the message must have R = 0 to avoid creating an out of sequence message that may cause the pager to indicate a missed message. * * Freescale Semiconductor, Inc... * * * * * * * * FLEX DECODING RULES * * FLEX decoding devices may implement either single-phase addressing or any-phase addressing. FLEX decoding devices that support the numeric vector type (V2V1V0 = 011) must also support the short message vector (V2V1V0 = 010) with the message type (t1t0) set to 00. FLEX decoding devices that support the alphanumeric vector type (V2V1V0 = 101) must support the numeric vector type (V2V1V0 = 011) and the short message vector (V2V1V0 = 010) with the message type (t1t0) set to 00. FLEX paging devices that implement any-phase and support the alphanumeric vector type (V2V1V0 = 101) must also support the short instruction vector (V2V1V0 = 001) with the instruction type (i2i1i0) set to 000. * A-18 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions * FLEX decoding devices must be capable of decoding frames at all of the following combinations of data rate and modulation mode. They are: 1600 bps, 2 level; 3200 bps, 2 level; 3200 bps, 4 level; 6400 bps, 4 level. FLEX decoding devices must be designed to tolerate 4 minute fragment separation times. * FLEX Character Sets and Rules ALPHANUMERIC CHARACTER SET Freescale Semiconductor, Inc... The following tables define the characters to be displayed in the FLEX Alphanumeric Message mode. Control characters that are not acted upon by the pager are ignored in the display process (do not require display space), but are stored in memory for possible download to an external device. Table A-13 Alphanumeric Character Set Least Significant 4 bits of character 0 1 2 3 4 5 6 7 8 9 A B C D E F Most Significant 3 bits of character 0 NUL SOH STX ETX EOT ENQ ACK BEL BS TAB LF VT FF CR SO SI 1 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US 2 SP ! " # $ % & ' ( ) * + , - . / 3 0 1 2 3 4 5 6 7 8 9 : ; < = > ? 4 @ A B C D E F G H I J K L M N O 5 P Q R S T U V W X Y Z [ \ ] ^ _ 6 ` a b c d e f g h i j k l m n o 7 p q r s t u v w x y z { | } ~ DEL MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-19 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions NUMERIC CHARACTER SET The following tables define the characters to be displayed in the FLEX Numeric Message mode. Table A-14 Standard Character Set (Peoples Republic of China Option Off) Character 0 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Freescale Semiconductor, Inc... 2 3 4 5 6 7 8 9 Spare U Space ] [ A-20 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-15 Alternate Character Set (Peoples Republic of China Option On) Character 0 1 2 3 4 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Freescale Semiconductor, Inc... 5 6 7 8 9 A B Space C D E MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-21 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions FLEX Local Time And Date The FLEX protocol allows for systems to transmit time information in its Block Information Field. When a system provider supports local time transmissions, the system provider is required, at a minimum, to transmit at least one time related block information word in each phase transmitted in frame 0, cycle 0. The time transmitted is the local time for the transmitted time zone and refers to the actual time at the leading edge of the first bit of Sync 1 of Frame 0 of the current cycle. The information carried in the s bits of the block information word depend on the value of the f bits of the block information word. The following sections describe the bit definitions of the time related block information words. Freescale Semiconductor, Inc... MONTH/DAY/YEAR Table A-16 Month/Day/Year Block Information Word Definition f2f1f0 001 Note: s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 m3 m2 m1 m0 d4 d3 d2 d1 d0 Y4 Y3 Y2 Y1 Y0 m = Month field--0001 through 1100 (binary) correspond to January through December, respectively d = Day field--00001 through 11111 (binary) correspond to 1 through 31, respectively Y = Year field--This represents the year with modulo arithmetic. 00000 through 11111 (binary) representing 1994 through 2025, 2026 through 2057, etc. SECOND/MINUTE/HOUR Table A-17 Second/Minute/Hour Block Information Word Definition f2f1f0 010 Note: s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 S5 S4 S3 M5 M4 M3 M2 M1 M0 H4 H3 H2 H1 H0 S = Second field--This represents a coarse value of the seconds field. These bits represent the seconds in eighth of a minute (7.5 second) increments. 000 through 111 (binary) correspond to 0 through 52.5 seconds, respectively M = Minute field--000000 through 111011 (binary) correspond to 0 through 59, respectively H = Hour field--00000 through 10111 (binary) correspond to 0 through 23, respectively. A-22 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions ACCURATE SECONDS/DAYLIGHT SAVINGS TIME/TIME ZONE Table A-18 System Message Block Information Word Definition f2f1f0 101 Note: s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 S2 S1 S0 x 1. L0 z4 z3 z2 z1 z0 0 1 0 X Description System Message1 When the s3 s2 s1 s0 field is set to 0100 or 0101, the other s4 through s13 are defined as above. The system messages with the s3 s2 s1 s0 field set to some other value do not contain time related information. S = Accurate Seconds--This field provides a more accurate seconds reference and can be used to adjust the seconds to within 1 second. This field represents how much time should be added to the coarse seconds in sixty-fourth of a minute increments. L = Daylight Savings Time--When this bit is set, the time being transmitted is local standard time. When it is clear, the time being transmitted is Daylight Savings Time. z = Time Zone--These bits indicate the time zone for which the time is being transmitted. The offset from GMT is the offset for local standard time. The following table describes the values for z. 2. Freescale Semiconductor, Inc... Table A-19 Time Zone Values z4z3z2z1z0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 Time Zone GMT GMT + 0100 GMT + 0200 GMT + 0300 GMT + 0400 GMT + 0500 GMT + 0600 GMT + 0700 GMT + 0800 GMT + 0900 GMT + 1000 z4z3z2z1z0 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 Time Zone GMT + 1100 GMT + 1200 GMT + 0330 GMT + 0430 GMT + 0530 RESERVED GMT + 0545 GMT + 0630 GMT + 0930 GMT - 0330 GMT - 1100 z4z3z2z1z0 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Time Zone GMT - 1000 GMT - 0900 GMT - 0800 GMT - 0700 GMT - 0600 GMT - 0500 GMT - 0400 GMT - 0300 GMT - 0200 GMT - 0100 MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-23 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions FLEX CAPCODES In order to send messages to a FLEX decoding device, the FLEX service provider must know the device's address, the address type (single-phase, any-phase, or all-phase), the address's assigned phase, the address's assigned frame, and the address's battery cycle. This information is typically included in a FLEX CAPCODE. The assignment of CAPCODEs is regulated to prevent duplication of addresses on a system. Check with your FLEX service provider or other appropriate regulatory body for FLEX CAPCODE assignments. The following paragraphs describe what these parameters define. Freescale Semiconductor, Inc... The device address consists of one or two 21-bit words. A one-word address is called a short address, while a two-word address is called a long address. Address words are separated into ranges according to the following table Table A-20 Address Word Range Definition Type Idle Word (Illegal Address) Long Address 1 Short Address Long Address 3 Long Address 4 Short Address (Reserved) Info Service Address Network Address Temporary Address Operator Messaging Address Short Address (Reserved) Long Address 2 Idle Word (Illegal Address) Hexadecimal Value 000000 000001-008000 008001-1E0000 1E0001-1E8000 1E8001-1F0000 1F0001-1F27FF 1F2800-1F67FF 1F6800-1F77FF 1F7800-1F780F 1F7810-1F781F 1F7820-1F7FFE 1F7FFF-1FFFFE 1FFFFF A-24 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Long addresses are grouped into the sets listed in Table A-21. Table A-21 Long Address Sets Long Address Set 1-2 1-3 1-4 2-3 First Word Long Address 1 Long Address 1 Long Address 1 Long Address 2 Long Address 2 Second Word Long Address 2 Long Address 3 Long Address 4 Long Address 3 Long Address 4 Freescale Semiconductor, Inc... 2-4 The address type indicates how messages on a particular address can be delivered in multi-phase FLEX frames. Messages sent on single-phase addresses can only be delivered in a particular phase (a, b, c, or d). Messages sent on any-phase addresses can be delivered in any phase, but a single message is limited to a single phase per frame. Messages sent on all-phase addresses can be delivered in any phase, and a single message can be spread across multiple phases in a single frame. All-phase messaging is a future feature of FLEX and has not been completely defined. The assigned phase is required only for single-phase devices. It determines the phase (a, b, c, or d) in which the messages is sent. The assigned frame and battery cycle determine the frames in which the decoding device typically looks for messages (other system factors can cause the decoding device to look in other frames in addition to the typical frames). The battery cycle is a number between 0 and 7 and defines how often the decoding device looks for messages on the FLEX channel. For a given battery cycle, b, the decoding device looks in every 2b frames. Thus, an address with an assigned frame of 3 and a battery cycle of 5 typically looks for messages in frame 3 and every 32 frames thereafter (i.e., frames 3, 35, 67, and 99). The FLEX CAPCODE is defined to represent either a short or a long address. The short address is defined in the FLEX protocol as one code word on the RF channel and is represented by a 7-digit decimal field. The long address is defined in the FLEX protocol as two code words on the RF channel and is represented by a 9- or 10-digit decimal field. The long addresses in set 1-2 are represented by a 9-digit decimal field. The long addresses in sets 1-3, 1-4, 2-3, and 2-4 are represented by a 10-digit decimal field. An alphabetic character known as the "CAPCODE type" always precedes the 7-, 9-, or 10-digit decimal address field. The CAPCODE type indicates the type of address and distinguishes FLEX CAPCODEs from CAPCODEs of other paging protocols. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-25 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions CAPCODE TYPE Example CAPCODEs are shown in Table A-22. The CAPCODE type can be any of "A" through "L" or "U" through "Z". The CAPCODE types "A" through "L" indicate that the standard rules are used to derive the assigned frame and phase information from the address field. (See Standard Frame and Phase Embedding Rules on page A-27.) For these CAPCODE types, the battery cycle (indicated as a "b" in Example 1) is indicated by a single decimal digit "0" through "7" preceding the CAPCODE type. When the FLEX standard battery cycle of 4 (16-frame cycle) is used, the battery cycle digit is not required (see Example 2 in Table A-22). The CAPCODE types "U" through "Z" indicate that the standard frame and phase embedding rules were not used and additional information is required. The phase assignment can be derived from the CAPCODE type, as described in Table A-23 on page A-28. The 3-digit decimal frame assignment "000" through "127" (indicated by "fff" in example 3) and single digit decimal battery cycle "0" through "7" (indicated as a "b" in Example 3 in Table A-22) may precede this CAPCODE type. The frame and battery cycle fields are not required. When they are not included (see Example 4 in Table A-22), the paging device or the subscriber database must be accessed to determine the assigned frame and battery cycle. The extended CAPCODE is a regular CAPCODE with a 10-digit address field and preceded by an extra alphabetic character "P" through "S". These CAPCODEs are used to provide additional information required for roaming devices. Table A-22 FLEX CAPCODE Examples Example 1 2 3 4 Freescale Semiconductor, Inc... Short bA1234567 A1234567 fffbU1234567 U1234567 Long bA123456789 A123456789 fffbU123456789 U123456789 Extended RbA1234567890 RA1234567890 RfffbU1234567890 RU1234567890 By using the convention of 7 digits to represent short addresses, 9 digits to represent some of the long addresses in set 1-2, and 10 digits to represent the balance of long addresses, it is possible to differentiate between the different types of addresses. The range of the decimal address field consists of the numbers 1 through 5,370,810,366 where short and other single code word addresses fall below 2,031,615 and Long addresses are above 2,101,248. The goal in displaying a CAPCODE is to use the shortest form possible. Even though the non-standard form could represent a standard assignment, the standard form is chosen to indicate that it is a standard assignment. All CAPCODE forms, except Example 4 in Table A-22, contain the information required to send a message to a subscriber unit. A-26 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions STANDARD FRAME AND PHASE EMBEDDING RULES Maximum battery life in a FLEX decoding device is achieved when all of the addresses assigned to a device are in the same frame. For single-phase decoding devices, it is a requirement for all assigned addresses to be in the same phase. Normally, it is very desirable to spread the population of FLEX subscriber units on a system across all four phases of all 128 frames. Frame and phase spreading can be performed automatically as addresses are assigned sequentially by embedding that information into the 7-, 9-, and 10-digit decimal FLEX address. The standard procedure for deriving the phase and frame values from the CAPCODE starts by separating the 7-, 9-, or 10-digit decimal address portion (field to the right of the CAPCODE type) and performing a decimal to binary conversion. The Least Significant Bit (LSB) is labeled bit "0". The following bits "2 and 3" in order, specify phases 00, 01, 10, or 11 for phase 0,1,2,3 (a, b, c, d), and bits "4-10" represent frames "000" through "127". The frame and phase can also be derived from the 7-, 9-, or 10-digit decimal address by using modulo arithmetic (base 10) where: Phase = (Integer (Addr/4)) Modulo 4 Frame = (Integer (Addr/16)) Modulo 128 When these rules are used, and addresses are assigned in order, the phase increments after four consecutive addresses are assigned, while the frame is incremented after sixteen addresses are assigned. Freescale Semiconductor, Inc... CAPCODE ALPHA CHARACTER DEFINITION The alpha character in the FLEX CAPCODE indicates the type of decoding device to which the address is assigned. The types include single-phase, any-phase, or allphase. It also indicates if the address is the first, second, third, or fourth address in the subscriber unit (when addresses are assigned in order and follow standard rules), and specifies the rules for determining in which phase and frame the address is active. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-27 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Table A-23 Alpha Character Codes Standard Rules A--Single-phase Subtract 0 B--Single-phase Subtract 1 C--Single-phase Subtract 2 D--Single-phase Subtract 3 No Rules (Non-Standard Form) U--Single-phase, Phase 0 V--Single-phase, Phase 1 W--Single-phase, Phase 2 X--Single-phase, Phase 3 Y--Any-phase -- -- -- Z--All-phase -- -- -- Freescale Semiconductor, Inc... E--Any-phase, Subtract 0 F--Any-phase Subtract 1 G--Any-phase Subtract 2 H--Any-phase Subtract 3 I--All-phase Subtract 0 J--All-phase Subtract 1 K--All-phase Subtract 2 L--All-phase Subtract 3 The following rules apply: * The character "A" represents a single-phase subscriber unit using the standard rules for embedding phase and frame. The character "B" is similar to "A", except 1 is subtracted from the CAPCODE before applying the standard rule. Likewise, the characters "C" and "D" indicate that 2 or 3 is to be subtracted before applying the rule. Using these CAPCODE characters ensures that sequentially numbered CAPCODEs are assigned to a common phase and frame. These procedures modify the standard rules and are intended to simplify the order entry process for multiple address subscriber units. When addresses are assigned in order, the subtraction of 1, 2, or 3 ensures that the calculation for each additional address in a decoding device is referenced to the first address. Thus, all A, B, C, and D addresses are assigned to the same frame and phase. Alpha characters "E" through "H" and "I" through "L" represent any-phase and all-phase subscriber units where the subtract rule is modified to ensure that all addresses of a multiple address subscriber unit are in the same frame. For the cases where no rule is defined, the letters "U" through "X" indicate single-phase subscriber units assigned to phases 0 through 3 (phases a * * A-28 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions through d) with the frame and battery cycle explicitly displayed. "Y" and "Z" indicate non-standard addresses for any-phase and all-phase subscriber units. * If the subscriber unit contains only a single individual address and the user is content with the recommended 30 second battery cycle, then the letter "A", "E", or "I" is added as a prefix to the 7-, 9- or 10-digit address, where: - - - * "A" indicates a single-phase device. "E" indicates an any-phase device. "I" indicates an all-phase device. Freescale Semiconductor, Inc... If the unit were to be a two address unit where both addresses are individual addresses, then "A", "E", or "I" would again preface the address field of the first address. "B", "F", or "J" would preface the second address. The "B", "F", or "J" indicates that the address is a second address and it is to have the properties of the first address. This rule eliminates the need for an administrative operator or a salesperson to calculate a starting address, which would allow standard rules to always apply. In other cases, especially where a group address is to be included, it is very likely that the "U" through "Z" forms of the CAPCODE will be used so that the frame can be explicitly chosen to provide best battery life, and the required "same phase" operation can be met in the case of the single-phase units. * CAPCODE TO BINARY CONVERSION Short CAPCODE To convert a short address CAPCODE, the number 32,768 is added to the 7- digit decimal CAPCODE address (or to any CAPCODE less than 2,031,615). The resultant number is then converted to a 21-bit binary number, which then becomes the information bits of the (31,21) BCH code word transmitted over the air. Long CAPCODE 2,101,249 to 1,075,843,072 Long address set 1-2 is in this range. To convert a long address CAPCODE, the number 2,068,481 is subtracted from the CAPCODE address. The resultant number is then divided by 32,768 with the remainder, incremented by 1, being the 1st word of the long address. This is the same as calculating the ((CAPCODE - 2,068,481) modulo 32768) + 1. This value is converted to a 21-bit binary number, which becomes the information bits in the (31,21) BCH code word transmitted over the air as the 1st address word. The second word of the long address is determined by first calculating the integer portion of the (CAPCODE - 2,068,481) divided by 32,768. This value is then subtracted from 2,097,151 (equivalent to the ones complement of the value in binary), and converted to a 21-bit binary number, which becomes the information bits in the (31, 21) BCH code word transmitted over the air as the second address word. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-29 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Long CAPCODE 1,075,843,073 to 3,223,326,720 Long address sets 1-3 and 1-4 are in this range. The 1st word of the long address is calculated following the same rules for the long addresses set 1-2. The second long address word is determined by subtracting 2,068,481 from the CAPCODE, the resultant number is divided by 32,768 with the integer portion added to 1,933,312. This value is converted to a 21-bit binary number, which becomes the (31,21) BCH code word transmitted over the air as the second address word. Long CAPCODE 3,223,326,721 to 4,297,068,542 Long address set 2-3 is in this range. The first word is determined by subtracting 2,068,479 from the CAPCODE. The remainder of dividing by 32,768 is retained (i.e., modulo 32,768). This value is then added to 2,064,383 with the result converted to a 21-bit binary number, which becomes the information bits in the (31,21) BCH code word transmitted over the air as the 1st address word. The second word is determined by subtracting 2,068,479 from the CAPCODE and finding the integer portion after dividing by 32,768. This value is then added to 1,867,776 and converted to a 21-bit binary number, which becomes the (31,21) BCH code word transmitted over the air as the second address word. Freescale Semiconductor, Inc... BINARY TO CAPCODE CONVERSION With the address code word values that are transmitted over the air, the CAPCODE can be calculated by performing the inverse of the above-specified process. As an example, the short address code word is converted to decimal and the number 32,768 is subtracted to arrive at the 7-digit address portion of the CAPCODE. For the two word long address set 1-2, the address word 1 is first converted from binary to decimal. The second address word is then complemented, (or subtracted from 2,097,151 decimal) and converted to a decimal. This value is multiplied by 32,768, added to 2,068,480, and then added to address word 1. The result is the address portion of the FLEX CAPCODE. A-30 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions CAPCODE ASSIGNMENTS The Table A-24 defines the address usage assignment. All addresses not listed in this table are not defined and reserved for future use. Table A-24 CAPCODE Assignment Table CAPCODE Address Value 0,000,000,000 0,000,000,001 to 0,001,933,312 0,001,933,313 to 0,001,998,848 Illegal Short Addresses Illegal Reserved for Future Use Information Service Addresses Network Addresses Temporary Addresses Operator Messaging Addresses Reserved for Future Use Illegal Long Address Set 1-2 Uncoordinated Long Address Set 1-2 by Country1 Long Address Set 1-2 Global2 Long Address Set 1-3 Global2 Long Address Set 1-4 Global2 Long Address Set 2-3 by Country1 Long Address Set 2-3 Reserved Long Address Set 2-3 Info Service3 Global2 Long Address Set 2-3 Info Service3 by Country1 Long Address Set 2-3 Info Service3 World-Wide Use4 Reserved for Future Use Description Freescale Semiconductor, Inc... 0,001,998,849 to 0,002,009,087 0,002,009,088 to 0,002,025,471 0,002,025,472 to 0,002,029,567 0,002,029,568 to 0,002,029,583 0,002,029,584 to 0,002,029,599 0,002,029,600 to 0,002,031,614 0,002,031,615 to 0,002,101,248 0,002,101,249 to 0,102,101,250 0,102,101,251 to 0,402,101,250 0,402,101,251 to 1,075,843,072 1,075,843,073 to 2,149,584,896 2,149,584,897 to 3,223,326,720 3,223,326,721 to 3,923,326,750 3,923,326,751 to 4,280,000,00 4,280,000,001 to 4,285,000,000 4,285,000,001 to 4,290,000,000 4,290,000,001 to 4,291,000,000 4,291,000,001 to 4,297,068,542 Note: 1. 2. 3. 4. "by Country"--The addresses are coordinated within each country and with countries along borders. "Global"--The address is coordinated to be unique world-wide. "Info Service"--Rules governing the use of these addresses are not currently defined. "World Wide Use"--One thousand addresses are assigned to each country for world-wide use. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com A-31 Freescale Semiconductor, Inc. MC68181 FLEX Message Word Definitions Freescale Semiconductor, Inc... A-32 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. APPENDIX B SPI PACKETS All data communicated between the FLEX chip IC and the host MCU is transmitted on the SPI in 32-bit packets. Each packet consists of an 8-bit ID followed by 24 bits of information. The FLEX chip IC uses the SPI bus in Full Duplex mode. In other words, whenever a packet communication occurs, the data in both directions is valid packet data. Freescale Semiconductor, Inc... The SPI consists of a READY pin and four SPI pins (SS, SCK, MOSI, and MISO).The SS is used as a chip select for the FLEX chip IC. The SCK is a clock supplied by the host MCU. The data from the host is transmitted on the MOSI line. The data from the FLEX chip IC is transmitted on the MISO line. PACKET COMMUNICATION INITIATED BY THE HOST When the host sends a packet to the FLEX chip IC, it performs the following steps (see Figure B-1): 1. Select the FLEX chip IC by driving the SS pin low. 2. Wait for the FLEX chip IC to drive the READY pin low. 3. Send the 32-bit packet. 4. De-select the FLEX chip IC by driving the SS pin high. 5. Repeat steps 1 through 4 for each additional packet. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-1 Freescale Semiconductor, Inc. MC68181 Packet Communication Initiated by the FLEX chip IC SS READY SCK 1 2 4 3 MOSI MISO D31 D1 D0 D31 D1 D0 D31 D1 D0 Freescale Semiconductor, Inc... D31 D1 D0 D31 D1 D0 D31 D1 D0 High Impedance State AA1230 Figure B-1 Typical Multiple Packet Communications Initiated by the Host When the host sends a packet, it will also receive a valid packet from the FLEX chip IC. If the FLEX chip IC is enabled (See Checksum Packet on page B-6.) and has no other packets waiting to be sent, the FLEX chip IC will send a status packet. The host must transition the SS pin from high to low to begin each 32-bit packet. The FLEX chip IC must see a negative transition on the SS pin in order for the host to initiate each packet communication. PACKET COMMUNICATION INITIATED BY THE FLEX CHIP IC When the FLEX chip IC has a packet for the host to read, the following occurs (see Figure B-2): 1. The FLEX chip IC drives the READY pin low. 2. If the FLEX chip IC is not already selected, the host selects the FLEX chip IC by driving the SS pin low. 3. The host receives (and sends) a 32-bit packet. 4. The host de-selects the FLEX chip IC by driving the SS pin high (optional). B-2 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Packet Communication Initiated by the FLEX chip IC SS READY SCK 1 2 4 3 MOSI MISO D31 D1 D0 D31 D1 D0 D31 D1 D0 Freescale Semiconductor, Inc... D31 D1 D0 D31 D1 D0 D31 D1 D0 High Impedance State AA1230 Figure B-2 Typical Multiple Packet Communications Initiated by the FLEX chip IC When the host is reading a packet from the FLEX chip IC, it must send a valid packet to the FLEX chip IC. If the host has no data to send, it is suggested that the host send a Checksum Packet with all of the data bits set to 0 in order to avoid disabling the FLEX chip IC. (See Checksum Packet on page B-6.) Figure B-3 on page B-3 illustrates that it is not necessary to de-select the FLEX chip IC between packets when the packets are initiated by the FLEX chip IC. SS READY SCK MOSI MISO D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 High Impedance State AA1231 Figure B-3 Multiple Packet Communications Initiated by the FLEX chip IC with No De-select MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-3 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Map HOST-TO-DECODER PACKET MAP The upper 8 bits of a packet comprise the packet ID. The following table describes the packet ID's for all of the packets that can be sent to the FLEX chip IC from the host. Table B-1 Host-to-Decoder Packet ID Map Packet ID (Hexadecimal) 00 Checksum Configuration Control All Frame Mode Operator Message Address Enables Roaming Control Packet Timing Control Packet Reserved (Host should never send) Receiver Line Control Receiver Control Configuration (Off Setting) Receiver Control Configuration (Warm Up 1 Setting) Receiver Control Configuration (Warm Up 2 Setting) Receiver Control Configuration (Warm Up 3 Setting) Receiver Control Configuration (Warm Up 4 Setting) Receiver Control Configuration (Warm Up 5 Setting) Receiver Control Configuration (3200sps Sync Setting) Receiver Control Configuration (1600sps Sync Setting) Receiver Control Configuration (3200sps Data Setting) Receiver Control Configuration (1600sps Data Setting) Receiver Control Configuration (Shut Down 1 Setting) Receiver Control Configuration (Shut Down 2 Setting) Special (Ignored by FLEX chip IC) Frame Assignment (Frames 112 through 127) Frame Assignment (Frames 96 through 111) Packet Type Freescale Semiconductor, Inc... 01 02 03 04 05 06 07-E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C-F 20 21 B-4 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Map Table B-1 Host-to-Decoder Packet ID Map (Continued) Packet ID (Hexadecimal) 22 23 24 25 26 Packet Type Frame Assignment (Frames 80 through 95) Frame Assignment (Frames 64 through 79) Frame Assignment (Frames 48 through 63) Frame Assignment (Frames 32 through 47) Frame Assignment (Frames 16 through 31) Frame Assignment (Frames 0 through 15) Reserved (Host should never send) User Address Enable Reserved (Host should never send) User Address Assignment (User address 0) User Address Assignment (User address 1) User Address Assignment (User address 2) User Address Assignment (User address 3) User Address Assignment (User address 4) User Address Assignment (User address 5) User Address Assignment (User address 6) User Address Assignment (User address 7) User Address Assignment (User address 8) User Address Assignment (User address 9) User Address Assignment (User address 10) User Address Assignment (User address 11) User Address Assignment (User address 12) User Address Assignment (User address 13) User Address Assignment (User address 14) User Address Assignment (User address 15) Reserved (Host should never send) Freescale Semiconductor, Inc... 27 28-7 78 79-F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90-F MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-5 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Map DECODER-TO-HOST PACKET MAP The following table describes the packet ID's for all of the packets that can be sent to the host from the FLEX chip IC. Table B-2 Decoder-to-Host Packet ID Map Packet ID (Hexadecimal) 00 Block Information Word Address Vector or Message (ID is word number in frame) Reserved Roaming Status Packet Reserved Receiver Shutdown Status Reserved Part ID Packet Type Freescale Semiconductor, Inc... 01 02-57 58-5F 60 61-7D 7E 7F 80-FE FF HOST-TO-DECODER PACKET DESCRIPTIONS The following sections describe the packets of information sent from the host to the FLEX chip IC. In all cases the packets should be sent MSB first (Bit 7 of byte 3 = Bit 31 of the packet = MSB). Checksum Packet The Checksum Packet is used to ensure proper communication between the host and the FLEX chip IC. The FLEX chip IC exclusive-ORs the 24 data bits of every packet it receives (except the Checksum Packet and the special packet ID's $1C through $1F) with an internal checksum register. Upon reset and whenever the host writes a packet to the FLEX chip IC, the FLEX chip IC is disabled from sending any information to the host processor until the host processor sends a Checksum Packet with the proper Checksum Value (CV) to the FLEX chip IC. When the FLEX chip IC is disabled in this way, it prompts the host to read the Part ID Packet. Note that all other operation B-6 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions continues normally when the FLEX chip IC is "disabled". The FLEX chip IC is only disabled in the sense that the data can not be read from the FLEX chip IC, all other operations continue to function. Disabled only implies that data cannot be read, all other internal operations continue to function. When the FLEX chip IC is reset, it is disabled and the internal checksum register is initialized to the 24-bit part ID defined in the Part ID Packet. (See Part ID Packet on page B-43.) Every time a packet other than the Checksum Packet and the special packets 1C through 1F is sent to the decoder IC, the value sent in the 24 information bits is exclusive-ORed with the internal checksum register, the result is stored back to the checksum register, and the FLEX chip IC is disabled. If a Checksum Packet is sent and the CV bits match the bits in the checksum register, the FLEX chip IC is enabled. If a Checksum Packet is sent when the FLEX chip IC is already enabled, the packet is ignored by the FLEX chip IC, in which case a null packet having the ID and data bits set to 0 is suggested. If a packet other than the Checksum Packet is sent when the FLEX chip IC is enabled, the decoder IC will be disabled until a Checksum Packet is sent with the correct CV bits. When the host reads a packet out of the FLEX chip IC but has no data to send, the Checksum Packet should be sent so the FLEX chip IC will not be disabled. The data in the Checksum Packet could be a null packet, 32-bit stream of all 0s, since a Checksum Packet will not disable the FLEX chip IC. When the host re-configures the FLEX chip IC, the FLEX chip IC will be disabled from sending any packets other than the Part ID Packet until the FLEX chip IC is enabled with a Checksum Packet having the proper data. The ID of the Checksum Packet is 0. Table B-3 Checksum Packet Bit Assignments Byte 3 2 1 0 Note: Freescale Semiconductor, Inc... Bit 7 0 CV23 CV15 CV7 Bit 6 0 CV22 CV14 CV6 Bit 5 0 CV21 CV13 CV5 Bit 4 0 CV20 CV12 CV4 Bit 3 0 CV19 CV11 CV3 Bit 2 0 CV18 CV10 CV2 Bit 1 0 CV17 CV9 CV1 Bit 0 0 CV16 CV8 CV0 CV = Checksum Value MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-7 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions RESET Disables Itself Initializes Checksum Register to Part ID Value Freescale Semiconductor, Inc... Initiates Part ID Packet Waits for SPI Packet from Host Y Checksum Packet? N Y Enabled? Disables Itself N Packet Data Matches Checksum Register Data? Y Enables Itself AA1232 N Sets Checksum Register to the XOR of the Packet Data Bits with the Checksum Register Bits Figure B-4 FLEX chip IC Checksum Flow Chart Configuration Packet The Configuration Packet defines a number of different configuration options for the FLEX chip IC. Proper operation is not guaranteed if these settings are changed when B-8 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions decoding is enabled (i.e., the ON bit in the Control Packet is set). The ID of the Configuration Packet is 1. Table B-4 Configuration Packet Bit Assignments Byte 3 2 1 Bit 7 0 0 0 SME Bit 6 0 0 0 MOT Bit 5 0 0 0 COD Bit 4 0 0 0 MTE Bit 3 0 0 0 LBP Bit 2 0 0 0 0 Bit 1 0 OFD1 SP1 0 Bit 0 1 OFD0 SP0 0 Freescale Semiconductor, Inc... 0 OSCILLATOR FREQUENCY DIFFERENCE (OFD) These bits describe the maximum difference in the frequency of the 76.8 kHz oscillator crystal with respect to the frequency of the transmitter. These limits should be the worst case difference in frequency due to all conditions, including but not limited to aging, temperature, and manufacturing tolerance. Using a smaller frequency difference in this packet will result in lower power consumption due to higher receiver battery save ratios. Note that this value is not the absolute error of the oscillator frequency provided to the FLEX chip IC. The absolute error of the clock used by the FLEX transmitter must be taken into account. (If the transmitter tolerance is 25 ppm and the 76.8 kHz oscillator tolerance is 140 ppm, the oscillator frequency difference is 165 ppm and OFD should be set to 0.) The value after reset = 0. Table B-5 on page B-9 summarizes the bit definitions. Table B-5 OFD Bits Description OFD1 0 0 1 1 OFD0 0 1 0 1 Frequency Difference 300 ppm 150 ppm 75 ppm 0 ppm SIGNAL POLARITY (SP) These bits set the polarity of EXTS1 and EXTS0 input signals. The value after reset = 0. The polarity of the EXTS0 and EXTS1 bits will be determined by the receiver design. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-9 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Table B-6 SP Bit Definition SP1 0 0 1 1 SP0 0 1 0 1 Signal Polarity EXTS1 EXTS0 Normal Normal Inverted Inverted Normal Inverted Normal Inverted FSK Modulation @ SP = 0,0 +4800 Hz +1600 Hz -1600 Hz -4800 Hz EXTS1 1 1 0 0 EXTS0 0 1 1 0 Freescale Semiconductor, Inc... SYNCHRONOUS MODE ENABLE (SME) When this bit is set, a Status Packet will be automatically sent whenever the SMU (Synchronous Mode Update) bit in the Status Packet is set. The host can use the SM (Synchronous Mode) bit in the Status Packet as an in-range/out-of-range indication. The value after reset = 0. MAXIMUM OFF TIME (MOT) This bit has no effect if AST in the Timing Control Packet is non-zero. When AST = 0 and MOT = 0, asynchronous A-word searches will time-out in 4 minutes. When AST = 0 and MOT = 1, asynchronous A-word searches will time-out in 1 minute. (value after reset = 0) CLOCK OUTPUT DISABLE (COD) When this bit is clear, a 38.4 kHz signal will be output on the CLKOUT pin. When this bit is set, the CLKOUT pin will be driven low. Note that setting and clearing this bit can cause pulses on the CLKOUT pin that are less than one half the 38.4 kHz period. Also note that when the clock output is enabled, the CLKOUT pin will always output the 38.4 kHz signal even when the FLEX chip IC is in reset (as long as the FLEX chip IC oscillator is seeing clocks). The value after reset = 0. MINUTE TIMER ENABLE (MTE) When this bit is set, a Status Packet will be sent at one minute intervals with the MT (Minute Time-out) bit in the Status Packet set. When this bit is clear, the internal oneminute timer stops counting. The internal one-minute timer is reset when this bit is changed from 0 to 1 or when the MTC (Minute Timer Clear) bit in the Control Packet is set. The value after reset = 0. LOW BATTERY POLARITY (LBP) This bit defines the polarity of the FLEX chip ICs LOBAT pin. The LB bit in the Status Packet is initialized to the inverse value of this bit when the FLEX chip IC is turned on (by setting the ON bit in the Control Packet). When the FLEX chip IC is turned on, a low battery update is sent to the host in the Status Packet when a low battery condition is detected on the LOBAT pin. Setting this bit means that a high on the LOBAT pin indicates a low voltage condition. The value after reset = 0. B-10 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Control Packet The Control Packet defines a number of different control bits for the FLEX chip IC. The ID of the Control Packet is 2. Table B-7 Control Packet Bit Assignments Byte 3 2 Bit 7 0 FF7 0 0 Bit 6 0 FF6 SPM SBI Bit 5 0 FF5 PS1 0 Bit 4 0 FF4 PS0 MTC Bit 3 0 FF3 0 0 Bit 2 0 FF2 0 0 Bit 1 1 FF1 0 EAE Bit 0 0 FF0 0 ON Freescale Semiconductor, Inc... 1 0 FORCE FRAME (FF) 0-7 These bits enable and disable forcing the FLEX chip IC to look in frames 0 through 7. When an FF bit is set, the FLEX chip IC will decode the corresponding frame. Unlike the AF bits in the Frame Assignment Packets, the system collapse of a FLEX system will not affect frames assigned using the FF bits. (Where as setting AF0 to 1 when the system collapse is 5 will cause the decoder to decode frames 0, 32, 64, and 96, setting FF0 to 1 when the system collapse is 5 will only cause the decoder to decode frame 0.) This may be useful for acquiring transmitted time information or channel attributes (e.g. Local ID). The value after reset = 0. SINGLE PHASE MODE (SPM) When this bit is set, the FLEX chip IC will decode only one phase of the transmitted data. When this bit is clear, the FLEX chip IC will decode all of the phases it receives. A change to this bit while the FLEX chip IC is on, will not take affect until the next block 0 of the next decoded frame. The value after reset = 0. PHASE SELECT (PS) When the SPM bit is set, these bits define what phase the FLEX chip IC should decode according to the following table. This value is determined by the service provider. A change to these bits while the FLEX chip IC is on, will not take affect until the next block 0 of a frame. The value after reset = 0. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-11 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Table B-8 Phase Select Bit Definition PS Value PS1 0 0 1 Phase Decoded (based on FLEX Data Rate) 1600 bps a a a a PS0 0 1 0 1 3200 bps a a c c 6400 bps a b c d Freescale Semiconductor, Inc... 1 SEND BLOCK INFORMATION (SBI) WORDS 2-4 When this bit is set, any errored or time-related block information words 2-4 will be sent to the host. The value after reset = 0. MINUTE TIMER CLEAR (MTC) Setting this bit will cause the one minute timer to restart from 0. END OF ADDRESSES ENABLE (EAE) When this bit is set, the EA bit in the Status Packet will be set immediately after FLEX chip decodes the last address word in the frame if there was any address detected in the frame. When this bit is cleared, the EA bit will never be set. TURN ON DECODER (ON) Set if the FLEX chip IC should be decoding FLEX signals. Clear if signal processing should be off (very low power mode). If the ON bit is changed twice and the control packets making the changes are received within 2 ms of each other, FLEX chip may ignore the double change and stay in its original state (e.g. if it is turned off then on again within 2 ms it may stay on and ignore the off pulse). Therefore it is recommended that the host insures a minimum of 2 ms between changes in the ON bit. The value after reset = 0. Note: In order to properly turn off the decoder, the following steps must occur: 1. Turn off the FLEX chip by sending a Control Packet with the ON bit cleared. 2. Turn on the FLEX chip by sending a Control Packet with the ON bit set. 3. Turn off the FLEX chip by sending a Control Packet with the ON bit cleared. Timing between these steps is specified below and is measured from the positive edge of the last clock of one packet to the positive edge of the last clock of the next packet: B-12 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions * The minimum time between steps 1 and 2 is 2 ms or the programmed shut down time, whichever is greater. The programmed shut down time is the sum of all the of the times programmed in the used Receiver Shut Down Settings Packets. There is no maximum time between steps 1 and 2. The minimum time between steps 2 and 3 is 2 ms. The maximum time between steps 2 and 3 is the programmed warm up time minus 2 ms. The programmed warm up time is the sum of all the of the times programmed in the used Receiver Warm Up Settings Packets. * * * Freescale Semiconductor, Inc... All Frame Mode Packet The All Frame Mode Packet is used to decrement temporary address enable counters by one, decrement the all frame mode counter by one, and/or enable or disable forcing All Frame mode. If All Frame mode is enabled, the FLEX chip IC will attempt to decode every frame and send a Status Packet with the EOF (End-Of-Frame) bit set at the end of every frame. All Frame mode is enabled if any temporary address enable counter is non-zero, or, the All Frame mode counter is non-zero, or, the force All Frame Mode bit is set. Both the All Frame mode counter and the temporary address enable counters can only be incremented internally by the FLEX chip IC and can only be decremented by the host. The FLEX chip IC will increment a temporary address enable counter whenever a short instruction vector is received assigning the corresponding temporary address. The FLEX chip IC will increment the All Frame mode counter whenever an alphanumeric, HEX / binary, or secure vector is received. When the host determines that a message associated with a temporary address, or a fragmented message has ended, then the appropriate temporary address counter or All Frame mode counter should be decremented by writing an All Frame Mode Packet to the FLEX chip IC in order to exit the All Frame mode, thereby improving battery life. Neither the temporary address enable counters nor the All Frame mode counter can be incremented past the value 127 or decremented past the value 0 (i.e., it will not roll over). The temporary address enable counters and the All Frame mode counter are initialized to 0 at reset and when the decoder is turned off. The ID of the All Frame Mode Packet is 3. Table B-9 All Frame Mode Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 DAF DTA15 DTA7 Bit 6 0 FAF DTA14 DTA6 Bit 5 0 0 DTA13 DTA5 Bit 4 0 0 DTA12 DTA4 Bit 3 0 0 DTA11 DTA3 Bit 2 0 0 DTA10 DTA2 Bit 1 1 0 DTA9 DTA1 Bit 0 1 0 DTA8 DTA0 MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-13 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions DECREMENT ALL FRAME (DAF) COUNTER Setting this bit decrements the All Frame mode counter by one. If a packet is sent with this bit clear, the All Frame mode counter is not affected. The value after reset = 0. FORCE ALL FRAME (FAF) MODE Setting this bit forces the FLEX chip IC to enter All Frame mode. If this bit is clear, the FLEX chip IC may or may not be in All Frame mode depending on the status of the All Frame mode counter and the temporary address enable counters. This may be useful in acquiring transmitted time information. The value after reset = 0. DECREMENT TEMPORARY ADDRESS (DTA) ENABLE COUNTER Freescale Semiconductor, Inc... When a bit in this word is set, the corresponding temporary address enable counter is decremented by 1. When a bit is cleared, the corresponding temporary address enable counter is not affected. When a temporary address enable counter reaches 0, the temporary address is disabled.The value after reset = 0. Operator Messaging Address Enable Packet The operator messaging address enable packet is used to enable and disable the builtin FLEX operator messaging addresses. Enabling and disabling operator messaging addresses does not affect what frames the decoder IC decodes. To decode the proper frames, the host must modify the FF bits in the Control Packet or the AF bits in the Frame Assignment Packets. The ID of the operator messaging address enable packet is 4. Table 2-10 System Address Enable Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 0 OAE15 OAE7 Bit 6 0 0 OAE14 OAE6 Bit 5 0 0 OAE13 OAE5 Bit 4 0 0 OAE12 OAE4 Bit 3 0 0 OAE11 OAE3 Bit 2 1 0 OAE10 OAE2 Bit 1 0 0 OAE9 OAE1 Bit 0 0 0 OAE8 OAE0 OPERATOR MESSAGING ADDRESS ENABLE (OAE) When a bit is set, the corresponding operator messaging address is enabled. When it is cleared, the corresponding operator messaging address is disabled. OAE0 through OAE15 corresponds to the operator messaging address values of $1F7810 through $1F781F respectively. The value after reset = 0. B-14 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Roaming Control Packet The Roaming Control Packet controls the features of the Roaming FLEX chip IC that allow implementation of a roaming device. The ID of the roaming control packet is 5. Table 1: Roaming Control Packet Bit Assignments Byte 3 Bit 7 0 IRS RND 0 Bit 6 0 NBC ABI 0 Bit 5 0 MCM SAS MFC1 Bit 4 0 IS1 DAS MFC0 Bit 3 0 SDF 0 0 Bit 2 1 RSP 0 0 Bit 1 0 SND 0 MCO1 Bit 0 1 CND 0 MCO0 Freescale Semiconductor, Inc... 2 1 0 IGNORE RE-SYNCHRONIZATION SIGNAL (IRS) When this bit is set, the FLEX chip will not go asynchronous when detecting an Ar or Ar signal during searches for A-words. It will merely report that the resynchronization signal was received by setting RSR to 1 in the Roaming Status packet. This allows the host to decide what to do when the paging device is synchronous to more than one channel and only one channel is sending the resynchronization signal. It also prevents the FLEX chip from losing synchronization when it detects the re-synchronization signal while the paging device is checking an unknown channel. This bit is set and cleared by the host. The value after reset = 0. NETWORK BIT CHECK (NBC) Setting this bit will enable reporting of the received network bit value (NBU and n) in the Roaming Status Packet. Setting this bit also makes the FLEX chip abandon a frame after the Frame Info word without synchronizing to the frame if the frame information word is uncorrectable or if the n bit in the frame information word is not set. If the FLEX chip IC was in synchronous mode when this occurred (probably due to synchronizing to a second channel), it will maintain synchronization to the original channel. If the FLEX chip IC was in asynchronous mode when this occurred, it will stay in asynchronous mode and end the A-word search. This is done to avoid synchronizing to a non-roaming channel when searching for roaming channels. This bit is set and cleared by the host. The value after reset = 0. MANUAL COLLAPSE MODE (MCM) When this bit is set, the FLEX chip behaves as if the system collapse was 7. FLEX chip will not apply the received system collapse to the AF bits. When this bit is set, the received system collapse is reported to the host via SCU and RSC in the Roaming Status Packet. This is so the host can modify the AF bits based on the system collapse of the channel. This bit is set and cleared by the host. (value after reset = 0) MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-15 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions INVERT EXTS1 (IS1) Setting this bit inverts the expected polarity of the EXTS1 pin from the way it is configured by SP1 in the Configuration Packet (e.g. if both IS1 and SP1 are set, the polarity of the EXTS1 pin is untouched). This bit is intended to be changed when a change in a channel changes the polarity of the received signal. This bit is set and cleared by the host. The value after reset = 0. STOP DECODING FRAME (SDF) Setting this bit causes the FLEX chip to stop decoding a frame without losing frame synchronization. This bit is set by the host, and cleared by FLEX chip once it has been processed. The packet with the SDF bit be sent must be sent after receiving the status packet with EA bit set. It must be sent within 40 ms of the end of block in which FLEX chip set the EA bit. The value after reset = 0. Freescale Semiconductor, Inc... RECEIVER SHUTDOWN PACKET ENABLE (RSP) When this bit is set, a Receiver Shutdown Packet will be sent whenever the receiver is shut down. The receiver shutdown packet informs the host that the receiver shutdown, and how long it will be before FLEX chip will automatically warm the receiver back up. The value after reset = 0. START NOISE DETECT (SND) Setting this bit while the FLEX chip is battery saving will cause it to warm-up the receiver, run a noise detect, and report the result of the noise detect via NDR in the Roaming Status Packet. This bit is set by the host, and cleared by FLEX chip once it has been processed. If the time comes for FLEX chip to warm up for automatically or the SAS bit is set while an SND is being processed, the noise detect will be abandoned and the abandoned noise detect result (NDR = 01) will be sent in the Roaming Status Packet. The value after reset = 0. CONTINUOUS NOISE DETECT (CND) Setting this bit will cause FLEX chip to do continuous noise detects during the decoded block data of a frame. The results of the noise detect will only be reported if noise is detected (NDR = 11). Only one noise detected result (NDR = 11) will be sent per block. If the FLEX chip has not completed a noise detect when it shuts down for the frame, that noise detect will be abandoned, but no abandon result (NDR = 01) will be sent. This bit is set and cleared by the host. (value after reset = 0) REPORT NOISE DETECTS (RND) Setting this bit will cause FLEX chip to report the results of the noise detects it does under normal asynchronous operation (when first turned on and when asynchronous). The results of the noise detect will be reported via NDR in the Roaming Status Packet. This bit is set and cleared by the host. The value after reset = 0. B-16 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions ALL BLOCK INFORMATION WORDS (ABI) When this bit is set, FLEX chip will send all received Block Information words 2-4 to the host. Note: Setting the SBI bit in the Control Packet only enables errored and real time clock related block info words. The value after reset = 0. START A-WORD SEARCH (SAS) Setting this bit while in asynchronous battery save mode will cause FLEX chip to warm-up the receiver, and run an A-word search. If, during the A-word search, the FLEX chip IC finds sufficient FLEX signal, it will enter synchronous mode and start decoding the frame. If the A-word search times-out without finding sufficient FLEX signal, it will battery save and continue doing periodic noise detects. The time-out for the A-word searches is controlled by the AST bits in the Timing Control Packet and the MOT bit in the Configuration Packet. The A-word search takes priority over noise detects. Therefore, if FLEX chip is performing an A-word search and the time comes to do automatic noise detect, the noise detect will not be performed. This bit is set by the host, and cleared by FLEX chip once it has been acted on. The value after reset = 0. Freescale Semiconductor, Inc... DISABLE A-WORD SEARCH (DAS) When this bit is set, an A-word search will not automatically occur after a noise detect in asynchronous mode finds FLEX signal. This includes automatic noise detects and noise detects initiated by the host by setting SND. FLEX chip will shut down the receiver after the noise detect completes regardless of the result. When this bit is cleared, A-word searches will occur after a noise detect finds signal in asynchronous mode. The value after reset = 0. MFC:MISSED FRAME CONTROL (MFC) These bits control the frames for which missing frame data (MS1, MFI, MS2, MBI, and MAW) is reported in the Roaming Status Packet. The value after reset = 0. Table 2-11 Missed Frame Control Bit Definitions MFC1 0 0 1 1 MFC0 0 1 0 1 Missing Frame Data Reported Never Only during frames 0 through 3 Only during frames 0 through 7 Always MAXIMUM CARRY ON (MCO) The value of these bits sets the maximum carry on that FLEX chip will follow. For example, if FLEX chip receives a carry on of 3 over the air and MCO is set to 1, FLEX chip will only carry on for one frame. The value after reset = 0. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-17 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Timing Control Packet The timing control packet gives the host control of the timing used when FLEX chip is in asynchronous mode. The packet ID for the timing control packet is 6. Table 2-12 Timing Control Packet Bit Assignments Byte 3 2 Bit 7 0 0 AST7 ABT7 Bit 6 0 0 AST6 ABT6 Bit 5 0 0 AST5 ABT5 Bit 4 0 0 AST4 ABT4 Bit 3 0 0 AST3 ABT3 Bit 2 1 0 AST2 ABT2 Bit 1 1 0 AST1 ABT1 Bit 0 0 0 AST0 ABT0 Freescale Semiconductor, Inc... 1 0 A-WORD SEARCH TIME (AST) The value of these bits sets the A-word search time for all asynchronous A-word searches in units of 80 ms (e.g. value of 1 is 80 ms, value of 2 is 160 ms, etc.) If the value is 0, FLEX chip defaults to the 1-minute (MOT = 1) or 4-minute (MOT = 0) A-word search time controlled by the MOT bit in the configuration packet. The value after reset = 0. ASYNCHRONOUS BATTERY-SAVE TIME (ABT) The value of these bits sets the battery save time (time from the beginning of one automatic noise detect to the beginning of the next automatic noise detect) in asynchronous mode in units of 80 ms (e.g. value of 1 is 80 ms, value of 2 is 160 ms, etc.) If the value is 0, the battery save time is set to the default value of 1.5 seconds. The minimum allowed ABT is 320 ms, therefore values of 1, 2, 3, and 4 are invalid. The value after reset = 0. Receiver Line Control Packet This packet gives the host control over the settings on the receiver control lines (S0-S7) in all modes except reset. In reset, the receiver control lines are in high impedance settings. The ID for the Receiver Line Control Packet is 15 (decimal). Table B-13 Receiver Line Control Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 0 FRS7 CLS7 Bit 6 0 0 FRS6 CLS6 Bit 5 0 0 FRS5 CLS5 Bit 4 0 0 FRS4 CLS4 Bit 3 1 0 FRS3 CLS3 Bit 2 1 0 FRS2 CLS2 Bit 1 1 0 FRS1 CLS1 Bit 0 1 0 FRS0 CLS0 B-18 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions FORCE RECEIVER SETTING (FRS) Setting a bit to one will cause the corresponding CLS bit in this packet to override the internal receiver control settings on the corresponding receiver control line (S0-S7). Clearing a bit gives control of the corresponding receiver control lines (S0-S7) back to the FLEX chip IC. The value after reset = 0. CONTROL LINE SETTING (CLS) If the corresponding FRS bit was set in this packet, these bits define what setting should be applied to the corresponding receiver control lines. The value after reset = 0. Freescale Semiconductor, Inc... Receiver Control Configuration Packets These packets allow the host to configure: * * * what setting is applied to the receiver control lines S0-S7, how long to apply the setting, and, when to read the value of the LOBAT input pin. For a more detailed description of how the FLEX chip IC uses these settings see Receiver Control Configuration Packets on page B-19. The FLEX chip IC defines twelve different receiver control settings. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e., the ON bit in the Control Packet is set). The IDs for these packets range from 16 to 27 (decimal). Table B-14 Receiver Off Setting Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 0 CLS7 ST7 Bit 6 0 0 CLS6 ST6 Bit 5 0 0 CLS5 ST5 Bit 4 1 0 CLS4 ST4 Bit 3 0 LBC CLS3 ST3 Bit 2 0 0 CLS2 ST2 Bit 1 0 0 CLS1 ST1 Bit 0 0 0 CLS0 ST0 LOW BATTERY CHECK (LBC) If this bit is set, the FLEX chip IC will check the status of the LOBAT port just before leaving this receiver state. The value after reset = 0. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-19 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions CONTROL LINE SETTING (CLS) This is the value to be output on the receiver control lines (S0-S7) for this receiver state. The value after reset = 0. STEP TIME (ST) This is the time the FLEX chip IC is to keep the receiver off before applying the first warm up state's receiver control value to the receiver control lines. The setting is in steps of 625 s. Valid values are 625 s (ST = $01) to 159.375 ms (ST = $FF). The value after reset = 625 s. Freescale Semiconductor, Inc... Receiver Warm Up Setting Packets Table B-15 Receiver Warm Up Setting Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 SE CLS7 0 Bit 6 0 0 CLS6 ST6 Bit 5 0 0 CLS5 ST5 Bit 4 1 0 CLS4 ST4 Bit 3 0 LBC CLS3 ST3 Bit 2 s2 0 CLS2 ST2 Bit 1 s1 0 CLS1 ST1 Bit 0 s0 0 CLS0 ST0 SETTING NUMBER (s) These bit define the receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. Table B-16 Setting Number Bit Combinations s2 0 0 0 1 1 s1 0 1 1 0 0 s0 1 0 1 0 1 Setting Name Warm Up 1 Warm Up 2 Warm Up 3 Warm Up 4 Warm Up 5 B-20 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions STEP ENABLE (SE) The receiver setting is enabled when the bit is set. If a step in the warm up sequence is disabled, the disabled step and all remaining steps will be skipped. The value after reset = 0. LOW BATTERY CHECK (LBC) If this bit is set, the FLEX chip IC will check the status of the LOBAT port just before leaving this receiver state. The value after reset = 0. CONTROL LINE SETTING (CLS) Freescale Semiconductor, Inc... This is the value to be output on the receiver control lines (S0-S7) for this receiver state. The value after reset = 0. STEP TIME (ST) This is the time the FLEX chip IC is to wait before applying the next state's receiver control value to the receiver control lines. The setting is in steps of 625 s. Valid values are 625 s (ST = $01) to 79.375 ms (ST = $7F). The value after reset = 625 s. 3200 sps Sync Setting Packets Table B-17 3200 sps Sync Setting Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 0 CLS7 0 Bit 6 0 0 CLS6 ST6 Bit 5 0 0 CLS5 ST5 Bit 4 1 0 CLS4 ST4 Bit 3 0 LBC CLS3 ST3 Bit 2 1 0 CLS2 ST2 Bit 1 1 0 CLS1 ST1 Bit 0 0 0 CLS0 ST0 LOW BATTERY CHECK (LBC) If this bit is set, the FLEX chip IC will check the status of the LOBAT port just before leaving this receiver state. The value after reset = 0. CONTROL LINE SETTING (CLS) This is the value to be output on the receiver control lines (S0-S7) for this receiver state. The value after reset = 0. STEP TIME (ST) This is the time the FLEX chip IC is to wait before expecting good signals on the EXTS1 and EXTS0 signals after warming up. The setting is in steps of 625 s. Valid values are 625 s (ST = $01) to 79.375 ms (ST = $7F). The value after reset = 625 s. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-21 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Receiver On Setting Packets Table B-18 Receiver On Setting Packet Bit Assignments Byte 3 2 1 Bit 7 0 0 CLS7 0 Bit 6 0 0 CLS6 0 Bit 5 0 0 CLS5 0 Bit 4 1 0 CLS4 0 Bit 3 s3 LBC CLS3 0 Bit 2 s2 0 CLS2 0 Bit 1 s1 0 CLS1 0 Bit 0 s0 0 CLS0 0 Freescale Semiconductor, Inc... 0 SETTING NUMBER (s) These bits define the receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for "s" that apply to this packet. Table B-19 Setting Number Bit Definitions s3 0 1 1 s2 1 0 0 s1 1 0 0 s0 1 0 1 Setting Name 1600 sps Sync 3200 sps Data 1600 sps Data LOW BATTERY CHECK (LBC) If this bit is set, the FLEX chip IC will check the status of the LOBAT port just before leaving this receiver state. The value after reset = 0. CONTROL LINE SETTING (CLS) This is the value to be output on the receiver control lines (S0-S7) for this receiver state. The value after reset = 0. B-22 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Receiver Shut Down Setting Packets Table B-20 Receiver Shut Down Setting Packet Bit Assignments Byte 3 2 1 Bit 7 0 SE CLS7 0 Bit 6 0 0 CLS6 0 Bit 5 0 0 CLS5 ST5 Bit 4 1 0 CLS4 ST4 Bit 3 1 LBC CLS3 ST3 Bit 2 0 0 CLS2 ST2 Bit 1 1 0 CLS1 ST1 Bit 0 s 0 CLS0 ST0 Freescale Semiconductor, Inc... 0 SETTING NUMBER (s) These bits define the receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for "s" that apply to this packet. Table B-21 Setting Number Bit Definitions s 0 1 Setting Name Shut Down 1 Shut Down 2 STEP ENABLE (SE) The receiver setting is enabled when the bit is set. If a step in the shut down sequence is disabled, all steps following the disabled step will be ignored. The value after reset = 0. LOW BATTERY CHECK (LBC) If this bit is set, the FLEX chip IC will check the status of the LOBAT port just before leaving this receiver state. The value after reset = 0. CONTROL LINE SETTING (CLS) This is the value to be output on the receiver control lines (S0-S7) for this receiver state. The value after reset = 0. STEP TIME (ST) This is the time the FLEX chip IC is to wait before applying the next state's receiver control value to the receiver control lines. The setting is in steps of 625 s. Valid values are 625 s (ST = $01) to 39.375 ms (ST = $3F). The value after reset = 625 s. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-23 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Frame Assignment Packets The FLEX protocol defines that each address of a FLEX pager is assigned a home frame and a battery cycle (see FLEX CAPCODES on page A-24). This information is determined by the service provider. The FLEX chip IC must be configured so that a frame that is assigned by one or more of the addresses' home frames and battery cycles has its corresponding configuration bit set. For example, if the FLEX chip IC has one enabled address and it is assigned to frame 3 with a battery cycle of 4, the AF bits for frames 3, 19, 35, 51, 67, 83, 99, and 115 should be set and the AF bits for all other frames should be cleared. Freescale Semiconductor, Inc... When the FLEX chip IC is configured for manual collapse mode by setting the MCM bit in the Roaming Control Packet, the FLEX chip IC will not apply the received system collapse to the AF bits. The host should set the AF bits for all frames that should be decoded on all channels. For example, if frames 0 and 64 should be decoded on one channel and frames 4, 36, 68, and 100 should be decoded on another channel, all six of the corresponding AF bits should be set. The host can then change the receiver's carrier frequency after the FLEX chip IC decodes frames 0, 36, 64, and 100. There are 8 Frame Assignment Packets. The Packet IDs for these packets range from 32 to 39 (decimal) Table B-22 Frame Assignment Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 0 AF15 AF7 Bit 6 0 0 AF14 AF6 Bit 5 1 0 AF13 AF5 Bit 4 0 0 AF12 AF4 Bit 3 0 0 AF11 AF3 Bit 2 f2 0 AF10 AF2 Bit 1 f1 0 AF9 AF1 Bit 0 f0 0 AF8 AF0 FRAME RANGE (f) This value determines which sixteen frames correspond to the sixteen AF bits in the packet according to the following table. At least one of these bits must be set when the FLEX chip IC is turned on by setting the ON bit in the control packet. The value after reset = 0. B-24 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions Table B-23 Frame Range Bit Definition f2 0 0 0 0 1 f1 0 0 1 1 0 0 1 1 f0 0 1 0 1 0 1 0 1 AF15 Frame 127 Frame 111 Frame 95 Frame 79 Frame 63 Frame 47 Frame 31 Frame 15 AF0 Frame 112 Frame 96 Frame 80 Frame 64 Frame 48 Frame 32 Frame 16 Frame 0 Freescale Semiconductor, Inc... 1 1 1 ASSIGNED FRAME (AF) If a bit is set, the FLEX chip IC will consider the corresponding frame to be assigned via an address's home frame and pager collapse. The value after reset = 0. User Address Enable Packet The User Address Enable Packet is used to enable and disable the 16 user address words. Although the host is allowed to change the user address words while the FLEX chip IC is decoding FLEX signals, the host must disable a user address word before changing it. The ID of the User Address Enable Packet is 120 (decimal). Table B-24 User Address Enable Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 0 UAE15 UAE7 Bit 6 1 0 UAE14 UAE6 Bit 5 1 0 UAE13 UAE5 Bit 4 1 0 UAE12 UAE4 Bit 3 1 0 UAE11 UAE3 Bit 2 0 0 UAE10 UAE2 Bit 1 0 0 UAE9 UAE1 Bit 0 0 0 UAE8 UAE0 When a User Address Enable (UAE) bit is set, the corresponding user address word is enabled. When it is cleared, the corresponding user address word is disabled. UAE0 corresponds to the user address word configured using a packet ID of 128, and UAE15 corresponds to the user address word configured using a packet ID of 143. The value after reset = 0. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-25 Freescale Semiconductor, Inc. MC68181 Host-to-Decoder Packet Descriptions User Address Assignment Packets The FLEX chip IC has sixteen user address words. Each word can be programmed to be a short address, part of a long address, or the first part of a network ID. The addresses are configured using the Address Assignment Packets. Each user address can be configured as long or short and tone-only or regular. Network ID's are short and regular. Although the host is allowed to send these packets while the FLEX chip IC is on, the host must disable the user address word by clearing the corresponding UAE bit in the User Address Enable Packet before changing any of the bits in the corresponding User Address Assignment Packet. This method allows for easy reprogramming of user addresses without disrupting normal operation. The IDs for these packets range from 128 to 143 (decimal). Table B-25 User Address Assignment Packet Bit Assignments Byte 3 2 1 0 Freescale Semiconductor, Inc... Bit 7 1 0 A15 A7 Bit 6 0 LA A14 A6 Bit 5 0 TOA A13 A5 Bit 4 0 A20 A12 A4 Bit 3 a3 A19 A11 A3 Bit 2 a2 A18 A10 A2 Bit 1 a1 A17 A9 A1 Bit 0 a0 A16 A8 A0 USER ADDRESS WORD NUMBER (a0-a3) This specifies which address word is being configured. Having all 0s in this field corresponds to Address Index zero (AI = 0) in the Address Packet received from the FLEX chip IC when an address is detected. (See Address Packet on page B-29.) LONG ADDRESS (LA) When this bit is set, the address is considered a long address. Both words of a long address must have this bit set. The first word of a long address must have an even user address word number and the second word must be in the address index immediately following the first word. Long addresses of the 2-3 and 2-4 set (See FLEX CAPCODES on page A-21) must be programmed to higher user address word numbers than long addresses of the 1-2, 1-3, and 1-4 set. TONE-ONLY ADDRESS (TOA) When this bit is set, the FLEX chip IC will consider this address a tone-only address and will not decode a vector word when the address is received. If the TOA bit of a long address word is set, the TOA bit of the other word of the long address must also be set. ADDRESS WORD (A0-A20) This is the 21 bit value of the address word. Valid FLEX messaging addresses or Network ID's may be used. B-26 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions DECODER-TO-HOST PACKET DESCRIPTIONS The following sections describe the packets of information that will be sent from the FLEX chip IC to the host. In all cases the packets are sent MSB first (Bit 7 of byte 3 = Bit 31 of the packet = MSB). The FLEX chip IC decides what data should be sent to the host. If the FLEX chip IC is disabled through the checksum feature (see Checksum Packet on page B-6), the Part ID Packet will be sent. Data Packets relating to data received over the air are buffered in the 32 packet transmit buffer. The Data Packets include Block Information Word Packets, Address Packets, Vector Packets, and Message Packets. Freescale Semiconductor, Inc... If the FLEX chip IC is enabled and a receiver shutdown packet is pending, the receiver shutdown packet will be sent. If there is no receiver shutdown packet pending, but there is a roaming status packet pending, the roaming status packet will be sent. If neither the receiver shutdown packet nor the roaming status packet is pending and there is data in the transmit buffer, a packet from the transmit buffer will be sent. Otherwise, the FLEX chip IC will send the Status Packet (which is not buffered). In the event of a buffer overflow, the FLEX chip IC will automatically stop decoding and clear the buffer. It is recommended that the Host be designed to empty the FIFO buffer every block with enough time left over to read a status packet. This would ensure that any applicable Status Packet would be received within 1 block of the new status being available. 32 32 32 Part ID Register Receive Shutdown Register Roaming Status Register MUX 32 x 32 Data Packet FIFO Transmit Buffer 32 32 SPI Transmit Register MISO Status Register 32 AA1233 Figure B-5 FLEX chip IC SPI Transmit Functional Block Diagram MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-27 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions Block Information Word Packet The Block Information Field is the first field following the synchronization codes of the FLEX protocol (see Appendix A). This field contains information about the frame, such as number of addresses and messages, information about current time, the channel ID, channel attributes, etc. The first block information word of each phase is used internally to the FLEX chip IC and is never transmitted to the host with the exception of the system collapse which is sent to the host when FLEX chip is in manual collapse mode. Freescale Semiconductor, Inc... Time block information words 2-4 can be optionally sent to the host by setting the SBI bit in the control packet. (see Control Packet on page B-11.) All block information words 2-4 can be optionally sent to the host by setting the ABI bit in the roaming control packet. When the SBI or ABI bit is set and any block information word is received with an uncorrectable number of bit errors, the FLEX chip will send the block information word to the host with the e bit set regardless of the value of the "f" field in the block information word. The FLEX chip IC does not support decoding of the vector and message words associated with the Data/System Message block info word (f = 101). The ID of a Block Information Word Packet is 0 (decimal). Table B-26 Block Information Word Packet Bit Assignments Byte 3 2 1 0 Note: Bit 7 0 e x s7 Bit 6 0 p1 x s6 Bit 5 0 p0 s13 s5 Bit 4 0 x s12 s4 Bit 3 0 x s11 s3 Bit 2 0 f2 s10 s2 Bit 1 0 f1 s9 s1 Bit 0 0 f0 s8 s0 e--set if more than 2 bit errors are detected in the word or if the check character calculation fails after error correction has been performed p--phase on which the block information word was found (0 = a, 1 = b, 2 = c, 3 = d) x--unused bits; the value of these bits is not guaranteed f--Word Format Type; the value of these bits modify the meaning of the s bits in this packet as described in the following table; if the e bit is not set, this field will be one of 001, 010, or 101 s--These are the information bits of the block information word. The definition of these bits depend on the f bits in this packet. Table B-27 on page B-29 describes the block information words that the FLEX chip IC decodes. Refer to Appendix A for detailed information about the time-related block information words (f = 001, 010, and 101). B-28 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions Table B-27 Block Information Word Definitions f2f1f0 000 001 010 011 100 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 i8 i7 i6 i5 i4 i3 i2 i1 i0 C4 C3 C2 C1 C0 . Description Local ID, Coverage Zone Month, Day, Year Second, Minute, Hour m3 m2 m1 m0 d4 d3 d2 d1 d0 Y4 Y3 Y2 Y1 Y0 S2 S1 S0 M5 M4 M3 M2 M1 M0 H4 H3 H2 H1 H0 Reserved by FLEX protocol for future use Reserved by FLEX protocol for future use z9 z8 z7 z6 z5 z4 z3 z2 z1 z0 A3 A2 A1 A0 System Message Freescale Semiconductor, Inc... 101 110 111 Reserved by FLEX protocol for future use c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 T3 T2 T1 T0 Country Code, Traffic Management Flags Address Packet The Address Field follows the Block Information Field in the FLEX protocol. See Appendix A for additional information. It contains all of the addresses in the frame. If less than three bit errors are detected in a received address word and it matches an enabled address assigned to the FLEX chip IC, an Address Packet will be sent to the host processor. The Address Packet contains assorted data about the address and its associated vector and message. The ID of an Address Packet is 1 (decimal). Table B-28 Address Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 PA AI7 TOA Bit 6 0 p1 AI6 WN6 Bit 5 0 p0 AI5 WN5 Bit 4 0 LA AI4 WN4 Bit 3 0 x AI3 WN3 Bit 2 0 x AI2 WN2 Bit 1 0 x AI1 WN1 Bit 0 1 x AI0 WN0 PRIORITY ADDRESS (PA) This bit is set if the address was received as a priority address. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-29 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions PHASE (p) These bits identify the phase on which the address was detected (0 = a, 1 = b, 2 = c, 3 = d). LONG ADDRESS TYPE (LA) This bit is set if the address was programmed in the FLEX chip IC as a long address. ADDRESS INDEX (AI) Valid values are 0 through 15 and 128 through 159. The index identifies which of the addresses was detected. Values 0 through 15 correspond to the sixteen programmable address words. Values 128 through 143 correspond to the sixteen temporary addresses. Values 144 through 159 correspond to the 16 operator messaging addresses. For long addresses, the address detect packet will only be sent once and the index will refer to the second word of the address. Freescale Semiconductor, Inc... TONE ONLY ADDRESS (TOA) This bit is set if the address was programmed in the FLEX chip IC as a tone-only address. This bit will never be set for temporary or operator messaging addresses. No vector word will be sent for tone-only addresses. WORD NUMBER (WN) OF VECTOR (2-87) These bits describe the location in the frame of the vector word for the detected address. This value is invalid for this packet if the TOA bit is set. UNUSED BITS (X) The value of these bits is not guaranteed. Vector Packet The Vector Field follows the Address Field (see Appendix A). Each Vector Packet must be matched to its corresponding Address Packet. The ID of the vector packet is the word number where the vector word was received in the frame. This value corresponds to the WN bits sent in the associated address packet. The phase information in both the Address Packet and the Vector Packet must also match. It is important to note for long addresses, the first message word will be transmitted in the word location immediately following the associated vector (See Message Building on page C-5). The word number (identified by b6-b0) in the Vector Packet will indicate the message start of the second message word if the message is longer than 1 word. There are several types of vectors: * Short Message/Tone Only Vector B-30 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions * * * * * Three types of Numeric Vectors Hex/Binary Vector Alphanumeric Vector Secure Message Vector Short Instruction Vector Each is described in the following pages. A detailed description of the FLEX software protocol requirements is provided in Appendix A. Four of the vectors (Hex/Binary, Alphanumeric, Secure Message, and Short Instruction) enable the FLEX chip IC to begin the All Frame mode. This mode is required to allow for the decoding of temporary addresses and/or fragmented messages. The host disables the All Frame mode after the proper time by writing to the decoder via the All Frame Mode Packet (see Building a Fragmented Message on page C-8). For any Address Packet sent to the host (except tone-only addresses), a corresponding Vector Packet will always be sent. If more than two bit errors are detected (via BCH calculations, parity calculations, check character calculations, or value validation) in the vector word the e bit will be set and the message words will not be sent. The Numeric, Hex/Binary, Alphanumeric, and Secure Message Vector Packets have associated Message Word Packets in the message field. The host must use the n and b bits of the vector word to calculate what message word locations are associated with the vector. Both the message word locations and the phase must match. One of the modes of the Short Instruction Vector is used for assigning temporary addresses that may be associated with a group call. Freescale Semiconductor, Inc... SHORT MESSAGE / TONE ONLY VECTOR Table B-29 Short Message / Tone Only Vector Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 e x d5 Bit 6 WN6 p1 x d4 Bit 5 WN5 p0 d11 d3 Bit 4 WN4 x d10 d2 Bit 3 WN3 x d9 d1 Bit 2 WN2 V2 d8 d0 Bit 1 WN1 V1 d7 t1 Bit 0 WN0 V0 d6 t0 MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-31 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions Table B-29 Short Message / Tone Only Vector Packet Bit Assignments (Continued) Byte Note: 1. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V: = 010 for a Short Message/Tone Only Vector WN--Word number of vector (2-87 decimal); describes the location of the vector word in the frame e--Set if more than 2 bit errors are detected in the word or, if after error correction, the check character calculation fails p--Phase on which the vector was found (0 = a, 1 = b, 2 = c, 3 = d) d--Data bits whose definition depend on the value of t in this packet according to the following table If this vector is received on a long address and the e bit in this packet is not set, the decoder will send a Message Packet from the word location immediately following the Vector Packet. Except for the short message on a non-network address (t = 0), all message bits in the Message Packet are unused and should be ignored Freescale Semiconductor, Inc... 2. Table B-30 Short Message / Tone Only Vector Definitions t1t0 00 01 10 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 s8 s7 s6 s5 s4 s3 s2 s1 s0 S2 S1 S0 s1 s0 R0 N5 N4 N3 N2 N1 N0 S2 S1 S0 . Description First 3 numeric chars1 8 sources (S) and 9 unused bits (s) 8 sources (S), message number (N), message retrieval flag (R)2, and 2 unused bits (s) spare message type 11 Note: 1. 2. 3. For long addresses, an extra 5 characters are sent in the Message Packet immediately following the Vector Packet. For a description of the R and N bits see the description of the same bits for numeric messages in Appendix A. t = Message type--These bits define the meaning of the "d" bits in this packet. x = Unused bits--The value of these bits is not guaranteed. NUMERIC VECTOR PACKET Table B-31 Numeric Vector Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 e x n0 Bit 6 WN6 p1 x b6 Bit 5 WN5 p0 K3 b5 Bit 4 WN4 x K2 b4 Bit 3 WN3 x K1 b3 Bit 2 WN2 V2 K0 b2 Bit 1 WN1 V1 n2 b1 Bit 0 WN0 V0 n1 b0 B-32 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions Vector Type Identifier (V) Table B-32 Numeric Vector Definitions V2V1V0 011 100 Name Standard Numeric Format Special Format Numeric Vector Description No special formatting of characters is specified. Formatting of the received characters is predetermined by special rules in the host. See FLEX Message Word Definitions on page A-7. The received information has been numbered by the service provider to indicate all messages have been properly received. Freescale Semiconductor, Inc... 111 Numbered Numeric Vector Additional Bit Descriptors Table B-33 Additional Bit Descriptor Definitions for Numeric Vector Packets Designator WN e Definition This is the Word Number of vector (2-87 decimal) that describes the location of the vector word in the frame. This bit is set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. These bits define the phase on which the vector was found (0 = a, 1 = b, 2 = c, 3 = d). These are the beginning check bits of the message. These bits define the number of words in the message including the second vector word for long addresses (000 = 1 word message, 001 = 2 word message, etc.). For long addresses, the first message word is located in the word location that immediately follows the associated vector. These bits define the word number of the message start in the message field (3-87 decimal). For long addresses, the word number indicates the location of the second message word. These are unused bits. The value of these bits is not guaranteed. p K n b x MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-33 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions HEX / BINARY, ALPHANUMERIC, AND SECURE MESSAGE VECTOR Table B-34 HEX / Binary, Alphanumeric, and Secure Message Vector Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 e x n0 Bit 6 WN6 p1 x b6 Bit 5 WN5 p0 n6 b5 Bit 4 WN4 x n5 b4 Bit 3 WN3 x n4 b3 Bit 2 WN2 V2 n3 b2 Bit 1 WN1 V1 n2 b1 Bit 0 WN0 V0 n1 b0 Freescale Semiconductor, Inc... Vector Type Identifier (V) Table B-35 Vector Type Identifier Definition V2V1V0 000 101 110 Type Secure Alphanumeric Hex / Binary Additional Bit Descriptors Table B-36 Additional Bit Descriptor Definitions for Numeric Vector Packets Designator WN e Definition This is the Word Number of vector (2-87 decimal) and it describes the location of the vector word in the frame. This bit is set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. These bits define the phase on which the vector was found (0 = a, 1 = b, 2 = c, 3 = d) These bits define the number of message words in this frame including the first Message word that immediately follows a long address vector. Valid values are 1- 85 decimal. Word number of message starts in the message field. Valid values are 3-87 decimal. Note: For long addresses, the first Message Packet is sent from the word location immediately following the word location of the Vector Packet. The b bits indicate the second message word in the message field if one exists. p n b x These are unused bits. The value of these bits is not guaranteed. B-34 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions SHORT INSTRUCTION VECTOR Table B-37 Short Instruction Vector Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 e x d4 Bit 6 WN6 p1 x d3 Bit 5 WN5 p0 d10 d2 Bit 4 WN4 x d9 d1 Bit 3 WN3 x d8 d0 Bit 2 WN2 V2 d7 i2 Bit 1 WN1 V1 d6 i1 Bit 0 WN0 V0 d5 i0 Freescale Semiconductor, Inc... Table B-38 Short Instruction Vector Packet Bit Descriptions Designator V WN e p d Description V = 001 for a Short Instruction Vector This indicates the Word Number of the vector (2-87 decimal) and describes the location of the vector word in the frame. This bit is set if more than 2 bit errors are detected in the word or, if after error correction, the check character calculation fails. These bits define the phase on which the vector was found. (0 = a, 1 = b, 2 = c, 3 = d) These are data bits whose definition depend on the "i" bits in this packet according to Table B-39. Note that if this vector is received on a long address and the "e" bit in this packet is not set, the decoder will send a Message Packet immediately following the Vector Packet. All message bits in the message packet are unused and should be ignored. Table B-39 Short Instruction Vector Definition i2i1i0 000 001 010 011 100 101 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 f6 f5 f4 f3 f2 f1 f0 Description Temporary address assignment1 Reserved Reserved Reserved Reserved Reserved MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-35 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions Table B-39 Short Instruction Vector Definition i2i1i0 110 111 Note: 1. 2. d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Reserved Description Reserved for test Assigned temporary address (a) and assigned frame (f). See Appendix C for additional information. i = Instruction type--These bits define the meaning of the d bits in this packet. x = Unused bits--The value of these bits is not guaranteed. Freescale Semiconductor, Inc... Message Packet The Message Field follows the Vector Field in the FLEX protocol. It contains the message data, checksum information, and may contain fragment numbers and message numbers. See Appendix A for additional information. If the error bit of a vector word is not set and the vector word indicates that there are message words associated with the page, the message words are sent in Message Packets. The ID of the Message Packet is the word number where the message word was received in the frame. Table B-40 Message Packet Bit Assignments Byte 3 2 1 0 Note: Bit 7 0 e i15 i7 Bit 6 WN6 p1 i14 i6 Bit 5 WN5 p0 i13 i5 Bit 4 WN4 i20 i12 i4 Bit 3 WN3 i19 i11 i3 Bit 2 WN2 i18 i10 i2 Bit 1 WN1 i17 i9 i1 Bit 0 WN0 i16 i8 i0 WN = Word number of message word (3-87 decimal)--Describes the location of the message word in the frame e is set if more than 2 bit errors are detected in the word. p = Phase on which the message word was found (0 = a, 1 = b, 2 = c, 3 = d) i = information bits of the message word--The definitions of these bits depend on the vector type and which word of the message is being received. See Appendix A for a detailed description of these bits. B-36 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions Roaming Status Packet The FLEX chip IC will prompt the host to read a Roaming Status Packet if RSR, MS1, MFI, MS2, MBI, MAW, NDR1, NDR0, NBU, or SCU is set. Table 1: Roaming Status Packet Bit Assignments Byte 3 2 Bit 7 0 RSR x x Bit 6 1 MS1 x x Bit 5 1 MFI x x Bit 4 0 MS2 x x Bit 3 0 MBI x SCU Bit 2 0 MAW x RSC2 Bit 1 0 NBU NDR1 RSC1 Bit 0 0 n NDR0 RSC0 Freescale Semiconductor, Inc... 1 0 RE-SYNCHRONIZATION SIGNAL RECEIVED (RSR) This bit is set when the FLEX chip detected a re-synchronization signal and the host configured FLEX chip to ignore it via the IRS bit in the roaming control packet. This bit is cleared when read. MISSED SYNCHRONIZATION 1 (MS1) This bit is set when the FLEX chip failed to detect the first synchronization pattern (A / A) of a FLEX frame and FLEX chip was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MISSED FRAME INFORMATION WORD (MFI) This bit is set when the frame information word is received with an uncorrectable number of errors and FLEX chip was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MISSED SYNCHRONIZATION 2 (MS2) This bit is set when the FLEX chip failed to detect the second synchronization pattern (C / C) of a frame and FLEX chip was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MISSED BLOCK INFORMATION WORD (MBI) This bit is set when at least one of the block information word ones is received with an uncorrectable number of errors and FLEX chip was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is set no more than once per frame regardless of the number of phases in the frame. This bit is cleared when read. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-37 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions MISSED ADDRESS WORD (MAW) This bit is set when any address words in the address field is received with an uncorrectable number of errors and FLEX chip was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is set no more than once per frame regardless of the number of address words in the frame. This bit is cleared when read. NETWORK BIT UPDATE (NBU) This bit is set when the NBC bit in the roaming control packet is set and a frame information word is received with a correctable number of errors. This bit will not be set when the frame information word is not received due to missing the first synchronization pattern (A / A). This bit is cleared when read. Freescale Semiconductor, Inc... NETWORK BIT VALUE (n) When NBU is set, this is the value of the n bit in the last received frame information word. NOISE DETECT RESULT (NDR) These bits indicate the result of a noise detect. The results of noise detects initiated by setting the SND bit in the roaming control packet will always be reported. The results of the automatic noise detects performed in asynchronous mode will only be reported if the RND bit is set in the roaming control packet. When continuous noise detects during block data are enabled by setting the CND bit in the roaming control packet, only the "No FLEX signal detected" result will be reported. These bits are cleared when read. Table 2-41 Noise Detect Result Bit Settings NDR 00 01 10 11 Noise Detect Result No Information Noise Detect was abandoned FLEX signal detected FLEX signal not detected SYSTEM COLLAPSE UPDATE (SCU) This bit is set when the FLEX chip IC is configured for manual collapse mode by setting the MCM bit in the roaming control packet and the system collapse of a frame is received. This bit is set no more than once per frame regardless of the number of phases in the frame. This bit will not be set in frames in which no block information word ones is received properly. This bit is cleared when read. B-38 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions RECEIVED SYSTEM COLLAPSE (RSC) When SCU is set, this value represents the system collapse value that was received in the frame. Receiver Shutdown Packet The Shutdown Packet is sent in both synchronous and asynchronous mode. It is designed to indicate to the host that the receiver is turned off and how much time there is until the FLEX chip will automatically turn it back on. Freescale Semiconductor, Inc... Table 2-42 Receiver Shut Down Packet Bit Assignments Byte 3 2 1 0 Bit 7 0 FNV TNF7 FCO Bit 6 1 CF6 TNF6 NAF6 Bit 5 1 CF5 TNF5 NAF5 Bit 4 1 CF4 TNF4 NAF4 Bit 3 1 CF3 TNF3 NAF3 Bit 2 1 CF2 TNF2 NAF2 Bit 1 1 CF1 TNF1 NAF1 Bit 0 0 CF0 TNF0 NAF0 FRAME NUMBER VALID (FNV) This bit is set if the last frame info word was correctable and the frame number was the expected value. When in asynchronous mode, this value will be 0. CURRENT FRAME (CF) When in synchronous mode, this is the current frame number. This value is latched on the negative edge of the READY line when this packet is sent to the host. The value of this field is valid only if the FLEX chip IC is in synchronous mode and the FIV bit in the status packet is set. When in asynchronous mode, this value will be 0. TIME TO NEXT FRAME (TNF) When in synchronous mode TNF indicates the time to the start of the A-word check if the FLEX chip IC were to warm up for the next frame. When in asynchronous mode TNF indicates the time to the start of the next automatic noise detect. See Using the Receiver Shutdown Packet on page C-12 for an explanation on how to use this value. This value is latched on the negative edge of the READY line when this packet is sent to the host. FRAME CARRIED ON FCO) This bit is set if the FLEX chip IC is decoding the next frame due to the reception of a non-zero carry-on value in a previous frame. When in asynchronous mode, this value will be 0. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-39 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions NEXT ASSIGNED FRAME (NAF) This is the frame number of next frame the FLEX chip IC was scheduled to decode when the receiver shut down. The value of this field is valid only if the FLEX chip IC is in synchronous mode and the FIV bit in the status packet is set. When in asynchronous mode this value will be 0. Status Packet The Status Packet contains various types of information that the host may require. The Status Packet will be sent to the host whenever the FLEX chip IC is polled and has no other data to send. The FLEX chip IC can also prompt the host to read the Status Packet due to events for which the FLEX chip IC was configured to send it (see Configuration Packet on page B-8 and Control Packet on page B-11 for a detailed description of the bits). The FLEX chip IC prompts the host to read a Status Packet if one of the following is true: * * * * * The MT bit in the Status Packet and the MTE bit in the Configuration Packet are set. The EOF bit in the Status Packet is set. The LBU bit in the Status Packet is set. The EA bit in the Status Packet is set. The BOE bit in the Status Packet is set. Freescale Semiconductor, Inc... The ID of the Status Packet is 127 (decimal) Table B-43 Status Packet Bit Assignments Byte 3 2 1 0 . Bit 7 0 FIV SM SMU Bit 6 1 f6 LB LBU Bit 5 1 f5 x x Bit 4 1 f4 x MT Bit 3 1 f3 c3 x Bit 2 1 f2 c2 EOF Bit 1 1 f1 c1 EA Bit 0 1 f0 c0 BOE FRAME INFO VALID (FIV) The FIV bit is set when a valid frame info word has been received since becoming synchronous to the system and the f and c fields contain valid values. If this bit is clear, no valid frame info words have been received since the FLEX chip IC became synchronous to the system. This value will change from 0 to 1 at the end of block 0 of the frame in which the 1st frame info word was properly received. It will be cleared when the FLEX chip IC goes into Asynchronous mode. This bit is initialized to 0 B-40 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions when the FLEX chip IC is reset and when the FLEX chip IC is turned off by clearing the ON bit in the Control Packet. CURRENT FRAME NUMBER (f) This value is updated every frame regardless of whether the FLEX chip IC needs to decode the frame. This value will change to its proper value for a frame at the end of block 0 of the frame. The value of these bits is not guaranteed when FIV is 0. SYNCHRONOUS MODE (SM) This bit is set when the FLEX chip IC is synchronous to the system. The FLEX chip IC will set this bit when the first synchronization words are received. It will clear this bit when synchronization to the FLEX signal is lost. This bit is initialized to 0 when the FLEX chip IC is reset and when it is turned off by clearing the ON bit in the Control Packet. Freescale Semiconductor, Inc... LOW BATTERY (LB) The LB bit is set to the value last read from the LOBAT pin. The host controls when the LOBAT pin is read via the Receiver Control Packets. This bit is initialized to 0 at reset. It is also initialized to the inverse of the LBP bit in the Configuration Packet when the FLEX chip IC is turned on by setting the ON bit in the Control Packet. CURRENT SYSTEM CYCLE NUMBER (c) This value is updated every frame regardless of whether the FLEX chip IC needs to decode the frame.This value will change to its proper value for a frame at the end of block 0 of the frame. The value of these bits is not guaranteed when FIV is 0. SYNCHRONOUS MODE UPDATE (SMU) The SM bit is set if the SM bit has been updated in this packet. When the FLEX chip IC is turned on, this bit will be set when the first synchronization words are found (SM changes to 1) or when the first synchronization search window after the FLEX chip IC is turned on expires (SM stays 0). The latter condition gives the host the option of assuming the paging device is in range when it is turned on, and displaying out-ofrange only after the initial A search window expires. After the initial Synchronous mode update, the SMU bit will be set whenever the FLEX chip IC transitions from/to Synchronous mode. Cleared when read. Changes in the SM bit due to turning off the FLEX chip IC will not cause the SMU bit to be set. This bit is initialized to 0 when the FLEX chip IC is reset. LOW BATTERY UPDATE (LBU) The LBU bit is set if the value on two consecutive reads of the LOBAT pin yielded different results and is cleared when read. The host controls when the LOBAT pin is read via the Receiver Control Packets. Changes in the LB bit due to turning on the FLEX chip IC will not cause the LBU bit to be set. This bit is initialized to 0 when the FLEX chip IC is reset. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-41 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions MINUTE TIME-OUT (MT) The MT bit is set if one minute has elapsed. The bit is cleared when read. This bit is initialized to 0 when the FLEX chip IC is reset. END OF FRAME (EOF) The EOF bit is set when the FLEX chip IC is in All Frame mode and the end of frame has been reached. The FLEX chip IC is in All Frame mode if the All Frames mode enable counter is non-zero, if any temporary address enabled counter is non-zero, or if the FAF bit in the All Frame Mode Packet is set. The bit is cleared when read. This bit is initialized to 0 when the FLEX chip IC is reset. Freescale Semiconductor, Inc... END OF ADDRESSES (EA) If EAE of the control packet is set and an address is detected in a frame, EA will be set after FLEX chip processes the last address in the frame. Since data packets take priority over the status packet, the status packet with the EA bit set is guaranteed to come after all address packets for the frame. This bit is cleared when read, and initialized to 0 when the FLEX chip IC is reset. BUFFER OVERFLOW ERROR (BOE) The BOE bit is set when information has been lost due to slow host response time. When the SPI transmit buffer on the FLEX chip IC overflows, the FLEX chip IC clears the transmit buffer, turns off decoding by clearing the ON bit in the Control Packet, and sets this bit. The bit is cleared when read. This bit is initialized to 0 when the FLEX chip IC is reset. UNUSED BITS (x) The value of these bits is not guaranteed. B-42 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions Part ID Packet The Part ID Packet is sent by the FLEX chip IC whenever the FLEX chip IC is disabled due to the checksum feature (see Checksum Packet on page B-6). Since the FLEX chip IC is disabled after reset, this is the first packet that will be received by the host after reset. The ID of the Part ID Packet is 255 (decimal). Table B-44 Part ID Packet Bit Assignments Byte Bit 7 1 MDL1 CID7 REV7 Bit 6 1 MDL0 CID6 REV6 Bit 5 1 CID13 CID5 REV5 Bit 4 1 CID12 CID4 REV4 Bit 3 1 CID11 CID3 REV3 Bit 2 1 CID10 CID2 REV2 Bit 1 1 CID9 CID1 REV1 Bit 0 1 CID8 CID0 REV0 Freescale Semiconductor, Inc... 3 2 1 0 MODEL (MDL) This identifies the FLEX chip model. Current value is 0. COMPATIBILITY ID (CID) This value describes what other parts with the same model number are compatible with this part. Current value is 3. Any future versions of FLEX chip that have MDL set to 0 and CID1 set to 1 will be 100% compatible to this version. CID0 is set to 1 because this chip is 100% backwards compatible to the standard FLEX chip. REVISION (REV) This identifies the revision and manufacturer of the FLEX chip. Currently defined values are as follows. Table B-45 FLEX chip Revisions REV 0,1,2,4 3 5 Pre-production Parts Motorola Semiconductor Products Sector Production Parts Texas Instruments Production Parts Description MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com B-43 Freescale Semiconductor, Inc. MC68181 Decoder-to-Host Packet Descriptions Freescale Semiconductor, Inc... B-44 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. APPENDIX C APPLICATION NOTES RECEIVER CONTROL Freescale Semiconductor, Inc... Introduction The FLEXchip IC has 8 programmable receiver control lines (S0-S7). The host has control of the receiver warm up and shut down timing, as well as all of the various settings on the control lines through configuration registers on the FLEXchip IC. The configuration registers for most settings allow the host to configure: * * * What setting is applied to the control lines, How long to apply the setting, and If the LOBAT input pin is polled before changing from the setting. With this programmability, the FLEXchip IC is able to interface with many off-theshelf receiver ICs. For details on the configuration of the receiver control settings, see Receiver Control Configuration Packets on page B-19. Receiver Settings at Reset The receiver control ports are tri-state outputs that are set to the high-impedance state when the FLEXchip IC is reset and until the corresponding FRS bit in the Receiver Line Control Packet is set, or until the FLEXchip IC is turned on by setting the ON bit in the Control Packet. This allows the designer to force the receiver control lines to the receiver off setting with external pull-up or pull-down resistors before the host can configure these settings in the FLEXchip IC. When the FLEXchip IC is turned on, the receiver control ports are driven to the settings configured by the Receiver Control Configuration Packets until the FLEXchip IC is reset again. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com C-1 Freescale Semiconductor, Inc. MC68181 Receiver Control Automatic Receiver Warm Up Sequence The FLEXchip IC allows for up to six steps associated with warming up the receiver. When the FLEXchip IC automatically turns on the receiver, it starts the warm up sequence 160 ms before it requires valid signals at the EXTS0 and EXTS1 input pins. The first step of the warm up sequence involves leaving the receiver control lines in the "Off" state for the amount of time programmed for "Warm Up Off Time". At the end of the "Warm Up Off Time", the first warm up setting, if enabled, is applied to the receiver control lines for the amount of time programmed for that setting. Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found. At the end of the last used warm up setting, the "1600 sps Sync Setting" or the "3200 sps Sync Setting" is applied to the receiver control lines depending on the current state of the FLEXchip IC. The sum total of all of the used warm up times and the "Warm Up Off Time" must not exceed 160 ms. If it exceeds 160 ms, the FLEXchip IC will execute the receiver shut down sequence at the end of the 160 ms warm up period. The receiver warm up sequence while decoding when all warm up settings are enabled.enabled is shown in Figure C-1 below.. 160 ms Warm Up Off Time Receiver Control Line Setting Off Warm Up Time 1 Warm Up Setting 1 Warm Up Time 2 Warm Up Setting 2 Warm Up Time 3 Warm Up Setting 3 Warm Up Time 4 Warm Up Setting 4 Warm Up Time5 Warm Up Setting 5 1600 sps or 3200 sps Sync Setting Freescale Semiconductor, Inc... Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check EXTS1 & EXTS0 Signals are Expected to be Valid Here AA1236 Figure C-1 Automatic Receiver Warm Up Sequence Host Initiated Receiver Warm Up Sequence The host can cause the FLEXchip IC to warm-up the receiver in three ways: * * * By turning on FLEXchip by setting the ON bit in the control packet By requesting a noise detect by setting the SND bit in the roaming control packet BY requesting an A-word search by setting the SAS bit in the roaming control packet C-2 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Receiver Control When the FLEXchip IC warms up the receiver in response to one of these host requests, the first warm up setting, if enabled, is applied to the receiver control lines for the amount of time programmed for that setting. Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found. Once a disabled warm up setting is found, the "3200sps Sync Setting" (for ON and SND warm ups) or the "1600sps Sync Setting" (for SAS warm ups) is applied to the receiver control lines and the decoder does not expect valid signal until after the "3200sps Sync Warm Up Time" (for ON, SND, and SAS warm ups) has expired. Figure C-2 shows the receiver warm up sequence when the host initiates a warm-up sequence, and when all warm up settings are enabled. Freescale Semiconductor, Inc... Warm Up Time 1 Receiver Control Line Setting Off Warm Up Setting 1 Warm Up Time 2 Warm Up Setting 2 Warm Up Time 3 Warm Up Setting 3 Warm Up Time 4 Warm Up Setting 4 Warm Up Time5 Warm Up Setting 5 3200 sps Sync Warm Up Time 3200 sps Sync Setting Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT EXTS1 & EXTS0 signals are Check expected to be valid here. AA1237 Figure C-2 Host Initiated Receiver Warm Up Sequence Receiver Shut Down Sequence The FLEXchip IC allows for up to three steps associated with shutting down the receiver. When the FLEXchip IC decides to turn off the receiver, the first shut down setting, if enabled, is applied to the receiver control lines for the corresponding shut down time. At the end of the last used shut down time, the "Off" setting is applied to the receiver control lines. If the first shut down setting is not enabled, the FLEXchip IC will transition directly from the current "On" setting to the "Off" setting. Figure C-3 shows the receiver turn off sequence when all shut down settings are enabled. If the receiver is on or being warmed up when the decoder is turned off (by clearing the ON bit in the Control Packet), the FLEXchip IC will execute the receiver shutdown sequence. If the FLEXchip IC is executing the shut down sequence when the FLEXchip IC is turned on (by setting the ON bit in the Control Packet), the FLEXchip IC will complete the shut down sequence before starting the warm up sequence. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com C-3 Freescale Semiconductor, Inc. MC68181 Receiver Control Shut Down Time 1 Receiver Control Line Setting 1600 sps or 3200 sps Sync or Data Setting Shut Down Setting 1 Shut Down Time 2 Shut Down Setting 2 Off Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check AA1238 Figure C-3 Receiver Shut Down Sequence Freescale Semiconductor, Inc... Miscellaneous Receiver States In addition to the Warm Up and Shut Down states, the FLEXchip IC has four other receiver states. When these settings are applied to the receiver control lines, the FLEXchip IC will be decoding the EXTS1 and EXTS0 input signals. The timing of these signals and their duration depends on the data the FLEXchip IC decodes. The four settings are as follows: * * * * 1600 sps Sync Setting--This setting is applied when the FLEXchip IC is searching for a 1600 symbols per second signal. 3200 sps Sync Setting--This setting is applied when the FLEXchip IC is searching for a 3200 symbols per second signal. 1600 sps Data Setting--This setting is applied after the FLEXchip IC has found the C or C sync word in a 1600 symbols per second frame. 3200 sps Data Setting--This setting is applied after the FLEXchip IC has found the C or C sync word in a 3200 symbols per second frame. Figure C-4 below shows some examples of how these settings will be used in the FLEXchip IC. C-4 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Message Building FLEX Signal Block 10 Sync 1 Frame Info Sync 2 Block 0 Receiver Control Line Setting Example #1 1600 sps Data or 3200 sps Data or Last Used Warm Up Setting 1600 sps Sync Setting 3200 sps Sync Setting 3200 sps Data Setting Possible LOBAT Check Receiver Control Line Setting Example #2 1600 sps Data or 3200 sps Data or Last Used Warm Up Setting Possible LOBAT Check 1600sps Sync Setting Possible LOBAT Check 1600 sps Data Setting Freescale Semiconductor, Inc... Possible LOBAT Check Possible LOBAT Check AA1239 Figure C-4 Examples of Receiver Control Transitions Low Battery Detection The FLEXchip IC can be configured to poll the LOBAT input pin at the end of every receiver control setting. This check can be enabled or disabled for each receiver control setting. If the poll is enabled for a setting, the pin will be read just before the FLEXchip IC changes the receiver control lines from that setting to another setting. The FLEXchip IC will send a Status Packet whenever the value on two consecutive reads of the LOBAT pin yields different results. MESSAGE BUILDING A simple message consists of an Address Packet followed by a Vector Packet indicating the word numbers of associated Message Packets.The tables below show a more complex example of receiving three Messages and two Block Information Word Packets in the first two blocks of a 2 phase 3200 bps, FLEX frame. Note: The messages shown may be portions of fragmented or group messages. Furthermore, in the case of a 6400 bps FLEX signal, there would be four phases: A, B, C and D, and in the case of a 1600 bps signal there would be only a single phase A. Table C-1 on page 6 shows the block number, Word Number (WN) and word content of both phases A and C. Note contents of words not meant to be received by the host are left blank. Each phase begins with a block information word (WN 0), that MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com C-5 Freescale Semiconductor, Inc. MC68181 Message Building is not sent to the host. The first message is in phase A and has an address (WN 3), vector (WN 7), and three message words (WN 9-11). The second message is also in phase A and has an address (WN 4), a vector (WN 8), and four message words (WN 12-15). The third message is in phase C and has a 2 word long address (WN 5-6) followed by a vector (WN 10) and three message words. Since the third message is sent on a long address, the first message word (WN 11) begins immediately after the vector. The vector indicates the location of the second and third message words (WN 14-15). Table C-1 FLEX SIGNAL Freescale Semiconductor, Inc... BLOCK 0 Word Number 0 1 3 4 5 6 7 PHASE A BIW1 PHASE C BIW1 BIW ADDRESS 1 ADDRESS 2 BIW LONG ADDRESS 3 WORD 1 LONG ADDRESS 3 WORD 2 VECTOR 1 VECTOR 2 MESSAGE 1, 1 MESSAGE 1, 2 MESSAGE 1, 3 MESSAGE 2, 1 MESSAGE 2, 2 MESSAGE 2, 3 MESSAGE 2, 4 MESSAGE 3, 2 MESSAGE 3, 3 VECTOR 3 MESSAGE 3, 1 1 8 9 10 11 12 13 14 15 Table C-2 on page C-7 shows the sequence of packets received by the host. The FLEXchip processes the FLEX signal one block at a time, and one phase at a time. Thus, the address and vector information in block 0 phase A is packetized and sent to the host in packets 1-3. Then information in block 0 phase C, two block information words and one long address, is packetized and sent to the host in packets 4-6. Packets 7-18 correspond to information in block 1, processed in phase A first and phase C second. C-6 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Message Building Table C-2 FLEXchip PACKET SEQUENCE PACKET 1st 2nd 3rd 4th PACKET TYPE ADDRESS ADDRESS VECTOR BIW BIW LONG ADDRESS VECTOR MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE VECTOR MESSAGE MESSAGE MESSAGE PHASE A A A C C C A A A A A A A A C C C C WORD NUMBER N.A. (7) N.A. (8) 7 N.A. N.A. N.A. (10) 8 9 10 11 12 13 14 15 10 11 14 15 COMMENT Address 1 has a vector located at WN 7. Address 2 has a vector located at WN 8. Vector for Address 1: Message Words located at WN = 9 to 11, phase A If BIWs enabled, then BIW packet sent If BIWs enabled, then BIW packet sent Long Address 3 has a vector beginning in word 10 of phase C. Vector for Address 2: Message Words located at WN = 12 to 15, phase A Message information for Address 1 Message information for Address 1 Message information for Address 1 Message information for Address 2 Message information for Address 2 Message information for Address 2 Message information for Address 2 Vector for Long Address 3: Message Words located at WN = 14-15, phase C Second word of Long Vector is first message information word of Address 3. Message information for Address 3 Message information for Address 3 Freescale Semiconductor, Inc... 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th 17th 18th The first message is built by relating packets 1, 3, and 8-10. The second message is built by relating packets 2, 7, and 11-14. The third message is built by relating packets 6 and 15-18. Additionally, the host may process block information in packets 4 and 5 for time setting information. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com C-7 Freescale Semiconductor, Inc. MC68181 Building a Fragmented Message BUILDING A FRAGMENTED MESSAGE The longest message that will fit into a frame is eighty-four code words total of message data. Three alpha characters per word yields a maximum message of 252 characters in a frame assuming no other traffic. Messages longer than this value must be sent as several fragments. Additional fragments can be expected when the "continue bit" in the 1st Message Word is set. This causes the pager to examine every following frame for an additional fragment until the last fragment with the continue bit reset is found. The only requirement relating to the placement in time of the remaining fragments is that no more than thirty-two frames (1 minute) or 128 frames (4 minutes) as indicated by the service provider may pass between fragment receptions. Each fragment contains a check sum character to detect errors in the fragment, a fragment number 0, 1, or 2 to detect missing fragments, a message number to identify which message the fragment is a part, and the continue bit, which either indicates that more fragments are in queue or that the last fragment has been received. All of this information is described in FLEX Message Word Definitions on page A-7. The following describes the sequence of events between the host and the FLEXchip IC required to handle a fragmented message: 1. The host receives a vector indicating one of the following types: Table C-3 Message Type Definition V2V1V0 000 101 110 Freescale Semiconductor, Inc... Type Secure Alphanumeric Hex / Binary 2. The FLEXchip IC increments the All Frame mode counter inside the FLEXchip IC and begin to decode all of the following frames. 3. The host receives the Message Packet(s) contained within that frame, followed by a Status Packet. The host must decide based on the Message Packet to return to normal decoding operation. If the message is indicated as fragmented by the Message Continued Flag "C" being set in the Message Packet for a Secure, Alphanumeric or Hex/Binary Message, then the host does not decrement the All Frame mode counter at this time. The host decrements the counter if the Message Continued Flag "C" is clear by writing the All Frame Mode Packet to the FLEXchip IC with the "DAF" bit = 1. If no other fragments, temporary addresses are pending or the FAF bit is clear in C-8 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Building a Fragmented Message the All Frame Mode Register, then the FLEXchip IC returns to normal operation. 4. The FLEXchip IC continues to decode all of the frames and passes any address information, vector information and message information to the host followed by a status packet indicating the end of the frame. If the message is indicated as fragmented by the Message Continued Flag "C" in the Message Packet for a Secure, Alphanumeric or Hex/Binary Message then the host remains in the Receive mode expecting more information from the FLEXchip IC. 5. After the host receives the second and subsequent fragment with the Message Continued Flag "C" = 1, it should decrement the All Frame mode counter by sending an All Frame Mode Packet to the FLEXchip IC with the "DAF" bit = 1. Alternatively, the host may choose to decrement the counter at the end of the entire message by decrementing the counter once for each fragment received. 6. When the host receives a Message Packet with the Message Continued Flag "C" = 0, it will send two All Frame Mode Packets to the FLEXchip IC with the "DAF" bit = 1. The two packets decrement the count for the first fragment and the last fragment. This decrements the All Frame mode counter to zero, if no other fragmented messages, or temporary addresses are pending or the FAF bit is clear in the All Frame Mode Register, and returns the FLEXchip IC to normal operation. 7. The above process must be repeated for each occurrence of a fragmented message. The host must keep track of the number of fragmented messages being decoded and insure the all frame mode counter decrements after each fragment or after each fragmented message. Table C-4 Alphanumeric Message Without Fragmentation PACKET 1st 2nd 3rd 4th Note: Freescale Semiconductor, Inc... PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE TBD PHASE A A A All Frame Counter 0 1 1 0 COMMENT Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 0; No more fragments are expected. Host writes All Frame Mode Packet to the FLEXchip IC with the "DAF" Bit = 1 TBD--Host Initiated Packet. The FLEXchip IC returns a packet according to Decoder-to-Host Packet Descriptions on page B-27. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com C-9 Freescale Semiconductor, Inc. MC68181 Building a Fragmented Message Table C-5 Alphanumeric Message with fragmentation PACKET 1st 2nd 3rd 4th PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE STATUS ADDRESS 1 VECTOR 1 MESSAGE TBD STATUS ADDRESS 1 VECTOR 1 MESSAGE TBD TBD PHASE A A A All Frame Counter 0 1 1 1 COMMENT Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 1, Message is fragmented, more expected End of Frame Indication (EOF = 1) Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 1, Message is fragmented, more expected. Host writes All Frame Mode Packet to the FLEXchip IC with the "DAF" bit = 1 End of Frame Indication (EOF = 1) Address 1 is received Vector = Alphanumeric type Message Word received "C" bit = 0, No more fragments are expected. Host writes All Frame Mode Packet to the FLEXchip IC with the "DAF" bit = 1 Host writes All Frame Mode Packet to the FLEXchip IC with the "DAF" bit = 1 Freescale Semiconductor, Inc... 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th Note: B B B 1 2 2 1 1 A A A 1 2 2 1 0 TBD--Host Initiated Packet. The FLEXchip IC returns a packet according to Decoder-to-Host Packet Descriptions on page B-27. C-10 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Operation of a Temporary Address OPERATION OF A TEMPORARY ADDRESS Group Messaging The FLEX protocol allows for a dynamic group call for the purpose of sending a common message to a group of paging devices. The dynamic group call approach assigns a "Temporary Address", using the personal address and the short instruction vector. The temporary address must be disabled by the host after the message is completed. Freescale Semiconductor, Inc... The FLEX protocol specifies sixteen addresses for the dynamic group call, which may be temporarily activated in a specific future frame (If the designated frame is equal to the present frame, the host is to interpret this as the next occurrence of this frame 4 minutes in the future.) The temporary address is valid for one message starting in the specified frame and remaining valid throughout the following frames to the completion of the message. If the message is not found in the specified frame (frame defined by a full 7-bit frame number), the host must disable the assigned temporary address. The following describes the sequence of events between the Host and the FLEXchip IC required to handle a temporary address: 1. Following an Address Packet, the host will receive a Vector Packet with V2V1V0 = 001 and i2i1i0 = 000 for a Short Instruction Vector indicating a temporary address has been assigned to this pager. The vector packet will indicate which temporary address is assigned and the frame in which the temporary address is expected. 2. The FLEXchip IC will increment the corresponding temporary address counter and begin to decode all of the following frames. 3. The FLEXchip IC continues to decode all of the frames and passes any address information, vector information, and message information to the host, followed by a status packet indicating the end of each frame and the current frame number. 4. There are several scenarios that may occur with temporary addresses. a. The temporary address is not found in the frame assigned and therefore the host must terminate the Temporary Address mode by sending an All Frame Mode Packet to the FLEXchip IC with the "DTA" bit of the particular temporary address set. b. The temporary address is found in the frame it was assigned and was not a fragmented message. Again, the host must terminate the Temporary Address mode by sending an All Frame Mode Packet to the FLEXchip IC with the "DTA" bit of the particular temporary address set. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com C-11 Freescale Semiconductor, Inc. MC68181 Using the Receiver Shutdown Packet c. The temporary address is found in the assigned frame and it is a fragmented message. In this case, the host must follow the rules for Operation of a Fragmented Message and determine the proper time to stop the All Frame mode operation. In this case, the host must write to the "DAF" bit with a "1" and the appropriate "DTA" bit with a "1" in the All Frame Mode Register in order to terminate both the fragmented message and the temporary address. 5. The above operation is repeated for every temporary address. Freescale Semiconductor, Inc... USING THE RECEIVER SHUTDOWN PACKET Calculating Time Left The receiver shutdown packet gives timing information to the host. Two times are of particular interest when implementing a roaming algorithm. * TimeToWarmUpStart is defined as the amount of time there is before the receiver will start to warm up (i.e. transition from the off state to the first warm up state). TimeToTasksDisabled is defined as the amount of time the host has to complete any host initiated tasks (e.g. by setting SND or SAS in the roaming control packet). The formulas for calculating these times depend on whether the FLEXchip is in synchronous mode or asynchronous mode. * * SYNCHRONOUS MODE: TimeToWarmUpStart ( TNF 80ms ) + ( SkippedFrames 1874.375ms ) + ReceiverOffTime - 167.5ms TimeToTasksDisabled ( TNF 80ms ) + ( SkippedFrames 1874.375ms ) - 247.5ms ASYNCHRONOUS MODE: TimeToWarmUpStart ( ( TNF - 2 ) 80ms ) + ReceiverOffTime TimeToTasksDisabled ( ( TNF - 3 ) 80ms ) C-12 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC68181 Using the Receiver Shutdown Packet Where TNF SkippedFrames Time to Next Frame. Value from the receiver shutdown packet. The number of frames that will not be decoded. This can be calculated from the Current Frame (CF) and Next Needed Frame (NAF) fields in the receiver shutdown packet (e.g. If CF is 10 and NAF is 12, then SkippedFrames is 1) The time programmed in the receiver off setting packet. ReceiverOffTime Freescale Semiconductor, Inc... Calculating How Long Tasks Take Since the TimeToTaskDisabled discussed in the previous section limits how much the host can do while the FLEXchip IC is battery saving, it is necessary for the host to know how long it can take the FLEXchip IC to perform a task. The formulas below calculate how long the two types of host initiated tasks take to complete as measured from the last SPI clock of the packet that initiates the task to the time the receiver shutdown sequence starts. Note that the receiver shutdown sequence must start before tasks are disabled. Noise Detect The following formula calculates how long it will take to complete a Noise Detect started by setting the SND bit in the roaming control packet. This formula assumes that (1) the noise detect was performed while in synchronous mode or (2) the noise detect was performed in asynchronous mode and did not find FLEX signal or (3) the noise detect found FLEX signal but the DAS bit of the roaming control packet was set. TimeToPerformNoiseDetect TotalWarmUpTime + 82ms Where TotalWarmUpTime The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. MOTOROLA MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com C-13 Freescale Semiconductor, Inc. MC68181 Using the Receiver Shutdown Packet The following formula calculates how long it will take to complete an A-word search initiated by setting the SAS bit in the roaming control packet. This formula assumes that the A-word search failed to find roaming FLEX channel. TimeToPerformAwordSearch TotalWarmUpTime + AST + 47ms Where TotalWarmUpTime The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. The value configured using the timing control packet. Freescale Semiconductor, Inc... AST Noise Detect / A-word Search The following formula calculates how long it will take to complete a Noise Detect/Aword search combination. This can occur when the noise detect is performed while in asynchronous mode, the noise detect finds FLEX signal, and the DAS bit of the roaming control packet is not set. TimeToPerformBoth TotalWarmUpTime + AST + 127ms Where TotalWarmUpTime The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. The value configured using the timing control packet. AST C-14 MC68181 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... FLEX, FLEXchip, FLEXstack, and Mfax are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 303-675-2140 1 (800) 441-2447 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Sinagawa-ku, Tokyo 141, Japan 81-3-5487-8488 MfaxTM: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 US & Canada ONLY (800) 774-1848 For More Information On This Product, Go to: www.freescale.com |
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